5秒后页面跳转
U74HCT7046G-S16-T PDF预览

U74HCT7046G-S16-T

更新时间: 2024-11-20 00:46:07
品牌 Logo 应用领域
友顺 - UTC /
页数 文件大小 规格书
16页 408K
描述
PHASE LOCKED LOOP WITH VCO & LOCK DETECTOR

U74HCT7046G-S16-T 数据手册

 浏览型号U74HCT7046G-S16-T的Datasheet PDF文件第2页浏览型号U74HCT7046G-S16-T的Datasheet PDF文件第3页浏览型号U74HCT7046G-S16-T的Datasheet PDF文件第4页浏览型号U74HCT7046G-S16-T的Datasheet PDF文件第5页浏览型号U74HCT7046G-S16-T的Datasheet PDF文件第6页浏览型号U74HCT7046G-S16-T的Datasheet PDF文件第7页 
UNISONIC TECHNOLOGIES CO., LTD  
U74HCT7046  
CMOS IC  
PHASE LOCKED LOOP WITH VCO &  
LOCK DETECTOR  
„
DESCRIPTION  
The U74HCT7046 is phase-locked-loop circuit that comprise a linear  
voltage-controlled oscillator (VCO), two-phase comparators (PC1, PC2),  
a lock detector, a common signal input amplifier and a common  
comparator input.  
The lock detector capacitor should be connected between pin  
15(CLD) and pin 8(GND).For a frequency range of 100kHz to 10MHz,the  
lock detector capacitor must be 1000pF to 10pF,respectively.  
The signal can be directly coupled to large voltage signals, or with a  
series capacitor coupled to small signals. Small voltage signals can be  
kept within the linear region of the input amplifiers with a self-bias input  
circuit. The U74HCT7046 and a passive low-pass filter form a  
second-order loop PLL. With a linear op-amp, the VCO achieves  
excellent linearity.  
The VCO requires external capacitor and resistor. R1 (between R1  
and GND) and capacitor C1 (between C1A and C1B) determine the  
frequency range of the VCO. R2 (between R2 and GND) enables the  
VCO to have a frequency offset if required.  
For the high input impedance of the VCO, the design of low-pass filters is simplified, and the designer has a wide  
choice of resistor/capacitor ranges. At pin 10 (DEMOUT), a demodulator output of the VCO input voltage is provided  
in order not to load the low-pass filter. In conventional techniques, the DEMOUT voltage is one threshold voltage  
lower than the VCO input voltage, but the DEMOUT voltage of U74HCT7046 equals the VCO input voltage. When  
DEMOUT is used, a load resistor (RS) should be connected from DEMOUT to GND; but if unused, DEMOUT should be  
left open. The VCO output (VCOOUT) can be connected directly or via a frequency-divider to the comparator input  
(COMPIN). If the VCO input is held at a constant DC level, the VCO output signal has a duty factor of 50%  
(maximum expected deviation 1%). A LOW level at the inhibit input (INH) enables the VCO and demodulator, while  
a HIGH level turns both off to minimize standby power consumption.  
„
FEATURES  
* Operating Power Supply Voltage Range: Digital Section 4.5 to 5.5 V  
VCO Section 4.5 to 5.5 V  
* Up to 18 MHz (typ.) Centre Frequency at VCC = 5V  
* Excellent VCO Frequency Linearity  
* VCO-Inhibit Control For ON/OFF Keying and for Low Standby Power Consumption  
* Minimal Frequency Drift  
* Zero Voltage Offset due to OP-Amp Buffering  
www.unisonic.com.tw  
1 of 16  
Copyright © 2012 Unisonic Technologies Co., Ltd  
QW-R502-851.A  

与U74HCT7046G-S16-T相关器件

型号 品牌 获取价格 描述 数据表
U74HCT7046L-P16-R UTC

获取价格

PHASE LOCKED LOOP WITH VCO & LOCK DETECTOR
U74HCT7046L-P16-T UTC

获取价格

PHASE LOCKED LOOP WITH VCO & LOCK DETECTOR
U74HCT7046L-S16-R UTC

获取价格

PHASE LOCKED LOOP WITH VCO & LOCK DETECTOR
U74HCT7046L-S16-T UTC

获取价格

PHASE LOCKED LOOP WITH VCO & LOCK DETECTOR
U74HCT73 UTC

获取价格

-0.5
U74HCU04 UTC

获取价格

-0.5v
U74LCX74 UTC

获取价格

LOW VOLTAGE DUAL D-TYPE POSITIVE EDGE-TRIGGERED FLIP-FLOP WITH 5V TOLERANT INPUTS
U74LCX74_15 UTC

获取价格

LOW VOLTAGE DUAL D-TYPE POSITIVE EDGE-TRIGGERED FLIP-FLO
U74LCX74G-P14-R UTC

获取价格

LOW VOLTAGE DUAL D-TYPE POSITIVE EDGE-TRIGGERED FLIP-FLOP WITH 5V TOLERANT INPUTS
U74LCX74G-P14-T UTC

获取价格

LOW VOLTAGE DUAL D-TYPE POSITIVE EDGE-TRIGGERED FLIP-FLOP WITH 5V TOLERANT INPUTS