U634H256
PowerStore 32K x 8 nvSRAM
Packages:PDIP32 (600 mil)
SOP32 (300 mil)
Transfers from the EEPROM to the
SRAM (the RECALL operation) take
place automatically on power up.
The U634H256 combines the high
performance and ease of use of a
fast SRAM with nonvolatile data
Features
High-performance CMOS non-
Description
volatile static RAM 32768 x 8 bits
25, 35 and 45 ns Access Times
10, 15 and 20 ns Output Enable
Access Times
ICC = 15 mA at 200 ns Cycle Time
Automatic STORE to EEPROM
on Power Down using external
capacitor
The U634H256 has two separate
modes of operation: SRAM mode
and nonvolatile mode. In SRAM
mode, the memory operates as an
ordinary static RAM. In nonvolatile
operation, data is transferred in
parallel from SRAM to EEPROM or
from EEPROM to SRAM. In this
mode SRAM functions are disab-
led.
integrity.
STORE cycles also may be initiated
under user control via a software
sequence or via a single pin (HSB).
Once a STORE cycle is initiated,
further input or output are disabled
until the cycle is completed.
Because a sequence of addresses
is used for STORE initiation, it is
important that no other read or write
accesses intervene in the sequence
or the sequence will be aborted.
RECALL cycles may also be initia-
ted by a software sequence.
Internally, RECALL is a two step
procedure. First, the SRAM data is
cleared and second, the nonvolatile
information is transferred into the
SRAM cells.
The RECALL operation in no way
alters the data in the EEPROM
cells. The nonvolatile data can be
recalled an unlimited number of
times.
Hardware or Software initiated
STORE
(STORE Cycle Time < 10 ms)
Automatic STORE Timing
105 STORE cycles to EEPROM
10 years data retention in
EEPROM
Automatic RECALL on Power Up
Software RECALL Initiation
(RECALL Cycle Time < 20 µs)
Unlimited RECALL cycles from
EEPROM
The U634H256 is a fast static RAM
(25, 35, 45 ns), with a nonvolatile
electrically
erasable
PROM
(EEPROM) element incorporated
in each static memory cell. The
SRAM can be read and written an
unlimited number of times, while
independent nonvolatile data resi-
des in EEPROM. Data transfers
from the SRAM to the EEPROM
(the STORE operation) take place
automatically upon power down
using charge stored in an external
100 µF capacitor.
Single 5 V ± 10 % Operation
Operating temperature ranges:
0 to 70 °C
-40 to 85 °C
CECC 90000 Quality Standard
ESD characterization according
MIL STD 883C M3015.7-HBM
(classification see IC Code
Numbers)
Pin Configuration
Pin Description
VCAP
A14
A12
A7
1
2
3
4
5
6
7
8
VCCX
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
Signal Name Signal Description
HSB
W
A0 - A14
Address Inputs
Data In/Out
A13
A8
DQ0 - DQ7
A6
A5
A9
Chip Enable
E
A4
A11
Output Enable
Write Enable
PDIP
SOP
G
A3
G
W
n.c.
A2
9
10
n.c.
A10
E
VCCX
VSS
VCAP
Power Supply Voltage
Ground
A1
A0
DQ0
DQ1
DQ2
VSS
11
12
13
14
15
16
DQ7
DQ6
DQ5
DQ4
DQ3
Capacitor
Hardware Controlled Store/Busy
HSB
Top View
1
December 12, 1997