U440/441
Vishay Siliconix
Matched N-Channel JFET Pairs
PRODUCT SUMMARY
Part Number VGS(off) (V) V(BR)GSS Min (V) gfs Min (mS) IG Typ (pA) jVGS1 – VGS2j Max (mV)
U440
U441
–1 to –6
–1 to –6
–25
–25
4.5
4.5
–1
–1
10
20
FEATURES
BENEFITS
APPLICATIONS
D Two-Chip Design
D High Slew Rate
D Minimum Parasitics Ensuring Maximum
D Wideband Differential Amps
High-Frequency Performance
D High-Speed, Temp-Compensated,
D Improved Op Amp Speed, Settling Time Accuracy
D Minimum Input Error/Trimming Requirement
D Insignificant Signal Loss/Error Voltage
D High System Sensitivity
Single-Ended Input Amps
D Low Offset/Drift Voltage
D Low Gate Leakage: 1 pA
D Low Noise
D High-Speed Comparators
D Impedance Converters
D High CMRR: 85 dB.
D Minimum Error with Large Input Signal
DESCRIPTION
The U440/441 are matched pairs of JFETs mounted in a single
TO-71 package. This two-chip design reduces parasitics and
gives better performance at very high frequencies while
ensuring extremely tight matching. These devices are an
excellent choice for use as wideband differential amplifiers in
demanding test and measurement applications.
The hermetically-sealed TO-71 package is available with full
military screening per MIL-S-19500 (see Military Information).
For similar products in SO-8 packaging see the
SST440/SST441 data sheet. For low-noise options, see the
SST/U401 series data sheet. For low-leakage alternatives,
see the U421/423 data sheet.
TO-71
S
G
2
1
1
3
6
4
D
1
D
2
2
5
G
1
S
2
Top View
ABSOLUTE MAXIMUM RATINGS
Gate-Drain, Gate-Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –25 V
Gate-Gate Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . "50 V
Gate Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . –55 to 150_C
a
Power Dissipation :
Per Side . . . . . . . . . . . . . . . . . . . . . . . . 250 mW
b
Total . . . . . . . . . . . . . . . . . . . . . . . . . . . 500 mW
Notes
1
Lead Temperature ( / ” from case for 10 sec.) . . . . . . . . . . . . . . . . . . . 300_C
16
a. Derate 2 mW/_C above 25_C
b. Derate 4 mW/_C above 25_C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65 to 200_C
Document Number: 70251
S-04031—Rev. D, 04-Jun-01
www.vishay.com
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