TSS4550
CTS and Serial input. Main UART operations are controlled and monitored by internal UART registers which are
available at the external bus interface. Line status is made available with each received data byte and stored in the
associated extra receive FIFO bits. Data transfers between the UART and FIFO are controlled by the Interface
Controller block.
There is no automatic flow control, so DTR, RTS, DSR, DCD and CTS should be managed by software as required.
If MODEM lines are not implemented, they can be used as general–purpose outputs or interrupt inputs.
There is no dedicated Ring Indicator input.
Multiplexer
The 1 to 3 multiplexer (see Figure 1. ) is used to route the UART serial input/output and MODEM input signals to and
from one of three ports: the IrDA 1.0 interface and two MODEM serial interfaces. The multiplexer is controlled by
two bits in the Interrupt Mask and Misc. Register (IMMR).
Only the UART serial data and input signals are multiplexed. These are the Serial output, Serial input, DCD, CTS and
DSR signals. The RTS and DTR signals for the two MODEM ports can be produced independently by software for each
port using the MODEM Control Register (MCR).
IrDA 1.0 Pulse Shaping
TSS4550 may directly drive an external IrDA 1.0 transceiver through an internal pulse shaping circuit. The function
is that of transmit pulse narrowing and receive pulse stretching. This unit generates transmit pulse widths of 1.6 µs
ths
nominal pulse width (3/16 bit time of the maximum bit rate of 115,200 bits/second). At all times, the pulse shaper
transmit output is kept in a state such that the transmit LED is normally off only being energized for the minimum
on–times during data transmission. The pulse shaping circuit is reset by the PSRST bit in the Control Register 1 (CR1)
or by the global hardware reset (RESET).
Interface Controller
The interface controller (see Figure 2. ) provides control and monitoring of the data transfers between the external bus
and FIFO and the UART and FIFO. It also allows the UART to be directly accessed by the external bus for UART control
and monitoring. Additional miscellaneous control functions are provided for features such as enabling of external
devices and parallel I/O.
It generates an external bus interrupt on the following conditions:
D Detection of an UART interrupt: changes in DSR, DCD or CTS, received characters with errors, break...
D Detection of receive FIFO becoming half–full.
D Detection of receive FIFO non–empty for longer than 3 character length times with no more characters being
received.
D Detection of transmit FIFO becoming half–empty.
D Detection of toggling inputs on MODEM port 1 when not selected
D Detection of toggling inputs on MODEM port 2 when not selected
The received serial data from the UART is written into the receive FIFO and made available to the external bus via
the FIFO Data Register (FDR – which is the output of the receive FIFO). The framing error and parity error bits
(available from the UART along with each received byte) are also stored in the receive FIFO. These status bits are made
available to the external bus in the Status Register (SR). When framing error or parity error information is needed, SR
must be read before FDR is read. When FDR is read, the next data byte and associated status bits are popped off the
FIFO so the SR locations are overwritten by the new status bits at the same time the data is available in FDR. If the
status bits for a data byte are not read before reading another data byte, the status bits for the first byte will be overwritten
with the status bits for the newly read data byte.
The receive FIFO will not be affected by external system reads whilst empty. An external read in these circumstances
will not change FDR and SR contents. The receive FIFO will also not accept any more data from the UART when full.
Rev. D – September 11, 1998
5
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