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TSS461CD PDF预览

TSS461CD

更新时间: 2024-01-18 12:33:18
品牌 Logo 应用领域
其他 - ETC 外围集成电路光电二极管数据传输控制器局域网时钟
页数 文件大小 规格书
52页 267K
描述
LAN Node Controller

TSS461CD 技术参数

是否无铅:含铅是否Rohs认证:不符合
生命周期:Obsolete零件包装代码:SOIC
包装说明:SOP,针数:24
Reach Compliance Code:compliantHTS代码:8542.31.00.01
风险等级:5.83Is Samacsys:N
地址总线宽度:8边界扫描:NO
最大时钟频率:8 MHz数据编码/解码方法:NRZ; BIPH-LEVEL(MANCHESTER)
最大数据传输速率:0.125 MBps外部数据总线宽度:8
JESD-30 代码:R-PDSO-G24长度:15.4 mm
低功率模式:YES湿度敏感等级:1
串行 I/O 数:1端子数量:24
最高工作温度:125 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):225认证状态:Not Qualified
座面最大高度:2.65 mm最大供电电压:5.5 V
最小供电电压:4.5 V标称供电电压:5 V
表面贴装:YES技术:CMOS
温度等级:AUTOMOTIVE端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30宽度:7.5 mm
uPs/uCs/外围集成电路类型:SERIAL IO/COMMUNICATION CONTROLLER, LANBase Number Matches:1

TSS461CD 数据手册

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TSS461C  
Vehicle Area Network Data Link Controller  
1. Description  
Cost optimization in car manufacturing is of extreme importance today. Solutions to this problem often implies the  
use of more advanced and intelligent electronic circuits.  
The TSS461C is such a circuit, which allows the transfer of all the status information needed in a car or truck over a  
single low-cost wire pair, thereby minimizing the electrical wire usage.  
It can be used to interconnect powerful functions (ABS, dashboard, power train control) and to control and interface  
car body electronics (lights, wipers, power window...).  
The TSS461C is fully compliant with the ISO standard ISO/11519-3. This standard supports a wide range of  
applications such as low-cost remote controlled switches, typically used for lamp control, up to complex, highly  
autonomous, distributed systems like engine controls, which require fast and secure data transfers.  
The TSS461C is a microprocessor interfaced line controller for mid to high complexity bus-masters and listeners like  
injection/ignition control calculators, dashboard controllers and car stereo or mobile telephone CPUs.  
The microprocessor interface consists of a 256 byte RAM and register area divided into 11 control registers, 14 channel  
register sets and 128 bytes of general purpose RAM, used as a message storage area, and a 6-source maskable interrupt.  
The circuit operates in the RAM using DMA techniques, controlled by the channel and control registers. This allows  
virtually any microprocessor to interface with ease to the TSS461C, and to use the free RAM as a scratch pad.  
Messages are encoded in enhanced Manchester code, and an optional pulsed code for use with an optical or radio link,  
at a maximum bit rate of 1 Mbit/s. The TSS461C analyzes the messages received or transmitted according to 6 different  
criterias including some higher level checks.  
In addition the bus interface has three separate inputs with automatic source diagnosis and selection, allowing for  
multibus listening or the automatic selection of the most reliable source at any time if several line receivers are  
connected to the same bus.  
2. Features  
D Fully compliant to VAN specification ISO/11519.3.  
D Handles all specified module types.  
D Handles all specified message types.  
D Handles retransmission of frames on contention and errors.  
D 3 separate line inputs with automatic diagnosis and selection.  
D 1 Mbit/s maximum transfer rate.  
D Normal or pulsed (optical and radio mode) coding.  
D INTEL, NEC, TI and MOTOROLA compatible 8-bit microprocessor interface.  
D Multiplexed address and data bus.  
D Idle and sleep modes.  
D 128 bytes of general purpose RAM.  
D DMA capabilities for message handling.  
D 14 identifier registers with all bits individually maskable.  
D 6-source maskable interrupt including an interrupt-on-reset to detect glitches on the reset pin.  
D Integrated crystal or resonator oscillator with internal baud rate generator and buffered clock output.  
D Single +5V power supply.  
D 0.8 µm CMOS technology.  
D SOP 24 packaging.  
Rev. D (22 Feb 01)  
1

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