Features
• Fully Compliant to VAN Specification ISO/11519.3
• Handles All Specified Module Types
• Handles All Specified Message Types
• Handles Retransmission of Frames on Contention and Errors
• 3 Separate Line Inputs with Automatic Diagnosis and Selection
• 1 Mbit/s Maximum Transfer Rate
• Normal or Pulsed (Optical and Radio Mode) Coding
• Intel®, NEC®, Texas Instruments® and Motorola® Compatible 8-bit Microprocessor
Interface
• Multiplexed Address and Data Bus
• Idle and Sleep Modes
• 128 Bytes of General-purpose RAM
• DMA Capabilities for Message Handling
• 14 Identifier Registers with All Bits Individually Maskable
• 6-source Maskable Interrupt Including an Interrupt-on-reset to Detect Glitches on the
Reset Pin
• Integrated Crystal or Resonator Oscillator with Internal Baud Rate Generator and
Buffered Clock Output
VAN Data Link
Controller
TSS461E
• Single +5V Power Supply
• 0.5 mm CMOS Technology
• SOP 24 Packaging
Advance
Information
Description
Cost optimization in car manufacturing is of extreme importance today. Solutions to
this problem often implies the use of more advanced and intelligent electronic circuits.
The TSS461E is a circuit which allows the transfer of all the status information needed
in a car or truck over a single low-cost wire pair, thereby, minimizing the electrical wire
usage.
It can be used to interconnect powerful functions (ABS, dashboard, power train con-
trol) and to control and interface car body electronics (lights, wipers, power window,
etc.).
The TSS461E is fully compliant with the ISO standard 11519-3. This standard sup-
ports a wide range of applications such as low-cost remote control switches, typically
used for lamp control; complex, highly-autonomous, distributed systems like engine
controls, which require fast and secure data transfers.
The TSS461E is a microprocessor-interfaced line controller for mid-to-high complexity
bus-masters and listeners like injection/ignition control calculators, dashboard control-
lers and car stereo or mobile telephone CPUs.
The microprocessor interface consists of a 256-bytes of RAM and the register area is
divided into 11 control registers, 14 channel register sets and 128 bytes of general
purpose RAM, used as a message storage area, and a 6-source maskable interrupt.
The circuit operates in RAM using DMA techniques, controlled by the channel and
control registers. This allows virtually any microprocessor to interface with ease to the
TSS461E, and to use the free RAM as a scratch pad.
Messages are encoded in enhanced Manchester code, and an optional pulsed code
for use with an optical or radio link, at a maximum bit rate of 1 Mbit/s. The TSS461E
analyzes the messages received or transmitted according to 6 different criteria includ-
ing some higher level checks.
In addition, the bus interface has three separate inputs with automatic source diagno-
sis and selection, allowing for multibus listening or the automatic selection of the most
reliable source at any time if several line receivers are connected to the same bus.
4194C–AUTO–01/06
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