Datasheet > TSS4550-CAB

TSS4550-CAB

更新时间： 2024-02-18 02:21:20

品牌	Logo	应用领域
TEMIC		/
页数	文件大小	规格书
31页	285K
描述
Serial I/O Controller, 3 Channel(s), 0.0140625MBps, CMOS, PQFP64, TQFP-64

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TSS4550-CAB 数据手册

TSS4550

Block Diagram

Bi–directional

FIFO

UART

D(7:0)

IrDA 1.2

Pulse shaping

IrDA Transceiver

A(3:0), control

Interface

controller

1:3

Multiplexer

MODEM Serial 1

MODEM Serial 2

Interrupt

Reset

External control

Parallel I/O

Reset

CLKout

clock PLL

32.768kHz

Figure 1. Block Diagram of TSS4550.

Pin Description

Function

Pins

Type

Rest

Description

State

Data bus

D[7:0]

I/O

I / low Data bus

strong

Address bus

A[3:0]

I / low Address bus

Bus interface control

ALE

I / low Address Latch Enable, address latched on falling edge

I / low Read strobe active high (must be tied low when not used)

I / high Read strobe active low (must be tied high when not used)

I / low Write strobe active high (must be tied low when not used)

I / high Write strobe active low (must be tied high when not used)

I / low Chip select active high (must be tied low when not used)

I / high Chip select active low (must be tied high when not used)

I / high Hardware reset, active low

RESET

INT

O / low Interrupt to external bus, active high

medium

Clocks

XTAL1

XTAL2

CLKOUT

IRRX

–

External crystal input

External crystal output

O / low Buffered clock

IrDA Interface

I / high From external IrDA transceiver – received data (inverted)

O / low To external IrDA transceiver – transmitted data

TXIR

medium

IRSD

RTS1

O / low External IrDA transceiver shutdown (when low) or general–purpose output,

active high

MODEM Serial 1

O / high MODEM 1 Request To Send or general–purpose output, active low

medium

Rev. D – September 11, 1998

Preliminary

123 4 5 6 7...31

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