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TSB83AA22C PDF预览

TSB83AA22C

更新时间： 2024-01-11 02:53:05
品牌 Logo 应用领域
德州仪器 - TI /
页数 文件大小 规格书
8页 147K
描述
Phy and OHCI Link Device

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中文翻译

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TSB83AA22C 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：BGA
包装说明：TFBGA,针数：168
Reach Compliance Code：compliantHTS代码：8542.31.00.01
Factory Lead Time：1 week风险等级：5.79
其他特性：NETWORK PROTOCOL= IEEE1394B地址总线宽度：
边界扫描：NO总线兼容性：PCI
最大时钟频率：33 MHz通信协议：ASYNC, BIT
最大数据传输速率：100 MBps外部数据总线宽度：
JESD-30 代码：S-PBGA-B168JESD-609代码：e1
长度：7 mm低功率模式：YES
湿度敏感等级：3串行 I/O 数：1
端子数量：168最高工作温度：70 °C
最低工作温度：封装主体材料：PLASTIC/EPOXY
封装代码：TFBGA封装形状：SQUARE
封装形式：GRID ARRAY峰值回流温度（摄氏度）：260
认证状态：Not Qualified座面最大高度：1.2 mm
最大供电电压：3.6 V最小供电电压：3 V
标称供电电压：3.3 V表面贴装：YES
技术：CMOS温度等级：COMMERCIAL
端子面层：Tin/Silver/Copper (Sn/Ag/Cu)端子形式：BALL
端子节距：0.5 mm端子位置：BOTTOM
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：7 mm
uPs/uCs/外围集成电路类型：SERIAL IO/COMMUNICATION CONTROLLER, SERIALBase Number Matches：1

TSB83AA22C 数据手册

 浏览型号TSB83AA22C的Datasheet PDF文件第2页浏览型号TSB83AA22C的Datasheet PDF文件第3页浏览型号TSB83AA22C的Datasheet PDF文件第4页浏览型号TSB83AA22C的Datasheet PDF文件第5页浏览型号TSB83AA22C的Datasheet PDF文件第6页浏览型号TSB83AA22C的Datasheet PDF文件第7页 
TSB83AA22C  
www.ti.com  
SLLS851–JUNE 2007  
TSB83AA22C IEEE Std 1394b-2002 Phy and OHCI Link Device  
FEATURES  
•
Fully Supports Provisions of IEEE Std  
1394b-2002 Revision 1.33+ at 1-Gigabit  
Signaling Rates  
•
•
Software Device Reset (SWR)  
Fail-Safe Circuitry Senses Sudden Loss of  
Power to the Device and Disables the Ports  
Ensure That the TSB83AA22C Does Not Load  
the TPBIAS of Any Connected Device and  
Blocks any Leakage From the Port Back to  
Power Plane  
•
Fully Supports Provisions of IEEE Std  
1394a-2000 and IEEE Std 1394-1995 Standards  
for High-Performance Serial Bus  
•
•
Fully Interoperable With Firewire™, i.LINK™,  
and SB1394 Implementations of IEEE Std 1394  
•
•
IEEE Std 1394a-2000-Compliant  
Common-Mode Noise Filter on Incoming Bias  
Detect Circuit to Filter Out Crosstalk Noise  
Provides Two Fully Backward-Compatible,  
IEEE Std 1394a-2000 Fully Compliant)  
Bilingual IEEE Std 1394b-2002 Cable Ports at  
up to 800 Megabits per Second (Mbps)  
Port Programmable to Force IEEE Std  
1394a-2000 Mode to Allow Use of IEEE Std  
1394a-2000 Connectors (IEEE Std 1394b-2002  
Signaling Must Not Be Put Across IEEE Std  
1394a-2000 Connectors or Cables)  
•
Full IEEE Std 1394a-2000 Support Includes:  
–
–
–
–
–
–
Connection Debounce  
Arbitrated Short Reset  
Multispeed Concatenation  
Arbitration Acceleration  
Fly-By Concatenation  
•
•
3.3-V and 5-V PCI Signaling Environments  
Serial-Bus Data Rates of 100 Mbps, 200 Mbps,  
400 Mbps, and 800 Mbps  
•
•
Physical Write Posting of up to Three  
Outstanding Transactions  
Port Disable/Suspend/Resume  
•
•
Extended Resume Signaling for Compatibility  
With Legacy DV Devices  
Serial ROM or Boot ROM Interface Supports  
2-Wire Serial EEPROM Devices  
Power-Down Features to Conserve Energy in  
Battery-Powered Applications  
•
•
33-MHz/32-Bit PCI Interface  
Multifunction Terminal (MFUNC Terminal 1):  
•
•
Low-Power Sleep Mode  
–
PCI_CLKRUN Protocol per the PCI Mobile  
Fully Compliant With Open Host Controller  
Interface (OHCI) Requirements  
Design Guide  
–
–
General-Purpose I/O  
•
•
Cable Power Presence Monitoring  
CYCLEIN/CYCLEOUT for External Cycle  
Timer Control for Customized  
Synchronization  
Cable Ports Monitor Line Conditions for  
Active Connection to Remote Node  
•
Register Bits Give Software Control of  
Contender Bit, Power-Class Bits, Link Active  
Control Bit, and IEEE Std 1394a-2000 Features  
•
PCI Burst Transfers and Deep FIFOs to  
Tolerate Large Host Latency:  
–
–
–
–
Transmit FIFO—5K Asynchronous  
Transmit FIFO—2K Isochronous  
Receive FIFO—2K Asynchronous  
Receive FIFO—2K Isochronous  
•
•
Interoperable With Other 1394 Physical Layers  
(Phy) Using 1.8-V, 3.3-V, and 5-V Supplies  
Low-Jitter, External Crystal Oscillator  
Provides Transmit and Receive Data at  
100/200/400/800 Mbps and Link-Layer  
Controller Clock at 49.152 MHz and  
98.304 MHz  
•
•
D0, D1, D2, and D3 Power States and PME  
Events per the PCI Bus Power Management  
Interface Specification  
Programmable Asynchronous Transmit  
•
Separate Bias (TPBIAS) for Each Port  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Firewire is a trademark of Apple Computer, Inc.  
i.LINK is a trademark of Sony Kabushiki Kaisha TA Sony Corporation.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
Copyright © 2007, Texas Instruments Incorporated  
12345678

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