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TS87C58X2-VJCB PDF预览

TS87C58X2-VJCB

更新时间： 2024-11-10 13:14:55
品牌 Logo 应用领域
爱特美尔 - ATMEL 微控制器
页数 文件大小 规格书
58页 962K
描述
Microcontroller, 8-Bit, OTPROM, 40MHz, CMOS, PQFP44, PLASTIC, QFP-44

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中文翻译

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TS87C58X2-VJCB 技术参数

是否无铅：不含铅是否Rohs认证：符合
生命周期：Transferred零件包装代码：QFP
包装说明：QFP,针数：44
Reach Compliance Code：compliantECCN代码：3A991.A.2
HTS代码：8542.31.00.01风险等级：5.39
Is Samacsys：N具有ADC：NO
地址总线宽度：16位大小：8
最大时钟频率：40 MHzDAC 通道：NO
DMA 通道：NO外部数据总线宽度：8
JESD-30 代码：S-PQFP-G44JESD-609代码：e3
长度：10 mmI/O 线路数量：32
端子数量：44片上程序ROM宽度：8
最高工作温度：85 °C最低工作温度：-40 °C
PWM 通道：NO封装主体材料：PLASTIC/EPOXY
封装代码：QFP封装形状：SQUARE
封装形式：FLATPACK峰值回流温度（摄氏度）：260
认证状态：Not QualifiedRAM（字节）：256
ROM（单词）：32768ROM可编程性：OTPROM
座面最大高度：2.4 mm速度：40 MHz
最大供电电压：5.5 V最小供电电压：4.5 V
标称供电电压：5 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：MATTE TIN端子形式：GULL WING
端子节距：0.8 mm端子位置：QUAD
处于峰值回流温度下的最长时间：40宽度：10 mm
uPs/uCs/外围集成电路类型：MICROCONTROLLERBase Number Matches：1

TS87C58X2-VJCB 数据手册

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TS80C54X2/C58X2  
TS87C54X2/C58X2  
8-bit CMOS Microcontroller 16/32 Kbytes ROM/OTP  
1. Description  
TS80C54/58X2 is high performance CMOS ROM, OTP The fully static design of the TS80C54/58X2 allows to  
reduce system power consumption by bringing the clock  
frequency down to any value, even DC, without loss of  
data.  
and EPROM versions of the 80C51 CMOS single chip  
8-bit microcontroller.  
The TS80C54/58X2 retains all features of the Atmel  
Wireless & Microcontrollers 80C51 with extended  
ROM/EPROM capacity (16/32 Kbytes), 256 bytes of  
internal RAM, a 6-source , 4-level interrupt system, an  
on-chip oscilator and three timer/counters.  
The TS80C54/58X2 has 2 software-selectable modes of  
reduced activity for further reduction in power  
consumption. In the idle mode the CPU is frozen while  
the timers, the serial port and the interrupt system are still  
operating. In the power-down mode the RAM is saved  
and all other functions are inoperative.  
In addition, the TS80C54/58X2 has a Hardware  
Watchdog Timer, a more versatile serial channel that  
facilitates multiprocessor communication (EUART) and  
a X2 speed improvement mechanism.  
2. Features  
● 80C52 Compatible  
● Interrupt Structure with  
•
•
•
•
8051 pin and instruction compatible  
Four 8-bit I/O ports  
•
•
6 Interrupt sources  
4 level priority interrupt system  
Three 16-bit timer/counters  
256 bytes scratchpad RAM  
● Full duplex Enhanced UART  
•
•
Framing error detection  
Automatic address recognition  
● High-Speed Architecture  
•
•
40 MHz @ 5V, 30MHz @ 3V  
● Low EMI (inhibit ALE)  
● Power Control modes  
X2 Speed Improvement capability (6 clocks/  
machine cycle)  
•
•
•
Idle mode  
30 MHz @ 5V, 20 MHz @ 3V (Equivalent to  
60 MHz @ 5V, 40 MHz @ 3V)  
Power-down mode  
Power-off Flag  
● Dual Data Pointer  
● Once mode (On-chip Emulation)  
● Power supply: 4.5-5.5V, 2.7-5.5V  
● On-chip ROM/EPROM (16K-bytes, 32K-bytes)  
● Programmable Clock Out and Up/Down Timer/  
Counter 2  
● Temperature ranges: Commercial (0 to 70oC) and  
Industrial (-40 to 85oC)  
● Hardware Watchdog Timer (One-time enabled with  
Reset-Out)  
● Packages: PDIL40, PLCC44, VQFP44 1.4, PQFP44  
F1, CQPJ44 (window), CDIL40 (window)  
● Asynchronous port reset  
Rev. C - 15 January, 2001  
1
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