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TPPM0115DRG4 PDF预览

TPPM0115DRG4

更新时间： 2024-11-05 15:54:59
品牌 Logo 应用领域
德州仪器 - TI 开关光电二极管
页数 文件大小 规格书
13页 235K
描述
0.5A SWITCHING CONTROLLER, 200kHz SWITCHING FREQ-MAX, PDSO8, GREEN, PLASTIC, SOIC-8

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中文翻译

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TPPM0115DRG4 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：SOIC
包装说明：SOP, SOP8,.25针数：8
Reach Compliance Code：unknownECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：5.21
模拟集成电路 - 其他类型：SWITCHING CONTROLLER控制模式：VOLTAGE-MODE
控制技术：HYSTERETIC CURRENT MODE最大输入电压：12.6 V
最小输入电压：11.4 V标称输入电压：12 V
JESD-30 代码：R-PDSO-G8JESD-609代码：e4
长度：4.9 mm湿度敏感等级：1
功能数量：1端子数量：8
最高工作温度：70 °C最低工作温度：
最大输出电流：0.5 A封装主体材料：PLASTIC/EPOXY
封装代码：SOP封装等效代码：SOP8,.25
封装形状：RECTANGULAR封装形式：SMALL OUTLINE
峰值回流温度（摄氏度）：260认证状态：Not Qualified
座面最大高度：1.75 mm子类别：Switching Regulator or Controllers
表面贴装：YES切换器配置：PUSH-PULL
最大切换频率：200 kHz温度等级：COMMERCIAL
端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)端子形式：GULL WING
端子节距：1.27 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：3.905 mm
Base Number Matches：1

TPPM0115DRG4 数据手册

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SLVS371A− MARCH 2001 − REVISED JUNE 2001  
SO (D) PACKAGE  
(TOP VIEW)  
features  
D
DC-DC Synchronous Buck Controller  
Switching Frequency, 200 kHz (Typ)  
V
GND  
SEN  
1
2
3
4
8
7
6
5
CC  
D
D
PWRGD  
NC  
Programmable Output Voltage,  
1 V to 2.5 V 2%  
DRVL  
DRVH  
PHASE  
D
D
D
Power Good Function (PWRGD)  
Input Voltage, 12 V 5%  
NC − No internal connection  
Drive High Load Current With External  
Components  
applications  
D
PC Motherboard, Voltage Regulation for  
System Power  
D
D
D
DDR Memory Supply (V  
or V  
)
TT  
DDQ  
RDRAM Memory Supply (V  
)
DDQ  
General Purpose Synchronous Switch  
Mode Controller  
description  
The TPPM0115 is a synchronous buck controller capable of driving two external power FETs 180° out of phase.  
The device requires a minimum of external standard filter components and switching FETs to regulate the  
desired output voltage. This is achieved with an internal switching frequency of 200 kHz (typical).  
The TPPM0115 switch mode controller and associated circuitry provide efficient voltage regulation of greater  
than 85%. The output voltage is set by two external resistors. During power up, when the output voltage reaches  
90% of the desired value, the power good (PWRGD) output is transitioned high after a short delay of 1 ms to  
5 ms. During power down, when the output voltage falls below 90% of the set value, the PWRGD output is pulled  
low without any delay.  
In the event the set output is in an over-voltage condition due to a system fault, the drive to the lower FET turns  
on to correct the fault. There is a dead time between switching one FET ON while the other FET is switching  
OFF to prevent cross conduction.  
The TPPM0115 is capable of driving high static load currents with minimal ripple on the output (<2%). The phase  
sense input is used to sense the flow of current through the inductor during flyback to minimize ripple on the  
output.  
To optimize output filter capacitance, the voltage mode control is based on a fixed ON time during the start of  
the cycle and hysteretic control during load transients. This allows the device to respond and maintain the set  
regulation voltage.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
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Copyright 2001, Texas Instruments Incorporated  
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...13

中文翻译

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TPPM0115DRG4 替代型号

型号 品牌 替代类型 描述 数据表
TPPM0115DR TI

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