TMS416400, TMS416400P, TMS417400, TMS417400P
TMS426400, TMS426400P, TMS427400, TMS427400P
4194304-WORD BY 4-BIT HIGH-SPEED DRAMS
SMKS881B – MAY 1995 – REVISED AUGUST 1995
DJ PACKAGE
(TOP VIEW)
DGA PACKAGE
(TOP VIEW)
Electrical characteristics for TMS416400/P and
TMS417400/P is Production Data. Electrical
characteristics
TMS427400/P is Product Preview only.
for
TMS426400/P
and
V
1
2
3
4
5
6
26
25
24
23
22
21
V
V
1
2
3
4
5
6
26
25
24
23
22
21
V
SS
CC
SS
CC
DQ1
DQ2
W
DQ4 DQ1
DQ3 DQ2
CAS
OE
A9
DQ4
DQ3
CAS
OE
Organization . . . 4194304 × 4
Single 5 V Power Supply for TMS41x400/P
(±10% Tolerance)
W
RAS
RAS
†
†
A11
A11
A9
Single 3.3 V Power Supply for
TMS42x400/P (±0.3 V Tolerance)
A10
A0
A1
A2
A3
8
19
18
17
16
15
14
A8
A7
A6
A5
A4
A10
A0
A1
A2
A3
8
19
18
17
16
15
14
A8
A7
A6
A5
A4
Performance Ranges:
9
9
ACCESS ACCESS ACCESS READ OR
10
11
12
13
10
11
12
13
TIME
TIME
TIME
WRITE
CYCLE
MIN
t
t
t
RAC
CAC
AA
MAX
MAX
MAX
’4xx400/P-60
’4xx400/P-70
’4xx400/P-80
60 ns
70 ns
80 ns
15 ns
18 ns
20 ns
30 ns
35 ns
40 ns
110 ns
130 ns
150 ns
V
V
V
V
SS
CC
SS
CC
Enhanced Page-Mode Operation With
CAS-Before-RAS (CBR) Refresh
Long Refresh Period and Self-Refresh
Option (TMS4xx400P)
PIN NOMENCLATURE
†
A0–A11
CAS
Address Inputs
3-State Unlatched Output
Low Power Dissipation
Column-Address Strobe
Data In/Data Out
DQ1–DQ4
OE
Output Enable
High-Reliability Plastic 24/26-Lead
300-Mil-Wide Surface-Mount Small-Outline
J-Lead (SOJ) Package and 24/26-Lead
Surface-Mount Thin Small-Outline Package
(TSOP)
NC
No Internal Connection
RAS
Row-Address Strobe
‡
V
V
5-V or 3.3-V Supply
Ground
CC
SS
W
Write Enable
Operating Free-Air Temperature Range:
†
‡
A11 is NC for TMS4x7400/P.
See Available Options Table
0°C to 70°C
EPIC (Enhanced Performance Implanted
CMOS) Technology
description
AVAILABLE OPTIONS
SELF
The TMS4xx400 is
a set of high-speed,
POWER
SUPPLY
REFRESH
CYCLES
REFRESH
BATTERY
BACKUP
DEVICE
16777216-bit dynamic random-access memories
organized as 4194304 words of 4 bits each. The
TMS4xx400P series are high-speed, low-power,
self-refresh, 16777216-bit dynamic random-
access memories organized as 4194304 words of
4 bits each. The TMS4xx400 and TMS4xx400P
employ state-of-the-art EPIC
Performance Implanted CMOS) technology for
high performance, reliability, and low power.
TMS416400
TMS416400P
TMS417400
TMS417400P
TMS426400
TMS426400P
TMS427400
TMS427400P
5 V
5 V
5 V
—
Yes
—
4096 in 64 ms
4096 in 128 ms
2048 in 32 ms
2048 in 128 ms
4096 in 64 ms
4096 in 128 ms
2048 in 32 ms
2048 in 128 ms
5 V
Yes
—
Yes
—
3.3 V
3.3 V
3.3 V
3.3 V
(Enhanced
Yes
These devices feature maximum RAS access times of 60 ns, 70 ns, and 80 ns. All addresses and data-in lines
are latched on-chip to simplify system design. Data out is unlatched to allow greater system flexibility.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
Copyright 1995, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
1
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