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TMS32C6416CGLZ6E3 PDF预览

TMS32C6416CGLZ6E3

更新时间: 2024-10-27 15:54:51
品牌 Logo 应用领域
德州仪器 - TI 时钟外围集成电路
页数 文件大小 规格书
137页 1944K
描述
64-BIT, 75.75MHz, OTHER DSP, PBGA532, 23 X 23 MM, 0.80 MM PITCH, PLASTIC, BGA-532

TMS32C6416CGLZ6E3 技术参数

是否Rohs认证:符合生命周期:Obsolete
零件包装代码:BGA包装说明:23 X 23 MM, 0.80 MM PITCH, PLASTIC, BGA-532
针数:532Reach Compliance Code:compliant
ECCN代码:3A001.A.3HTS代码:8542.31.00.01
风险等级:5.83Is Samacsys:N
地址总线宽度:23桶式移位器:NO
位大小:32边界扫描:YES
最大时钟频率:75.75 MHz外部数据总线宽度:64
格式:FIXED POINT内部总线架构:MULTIPLE
JESD-30 代码:S-PBGA-B532长度:23 mm
低功率模式:YES端子数量:532
最高工作温度:90 °C最低工作温度:
封装主体材料:PLASTIC/EPOXY封装代码:FBGA
封装等效代码:BGA532,26X26,32封装形状:SQUARE
封装形式:GRID ARRAY, FINE PITCH峰值回流温度(摄氏度):NOT SPECIFIED
电源:1.4,3.3 V认证状态:Not Qualified
RAM(字数):16384座面最大高度:3.3 mm
子类别:Digital Signal Processors最大供电电压:1.44 V
最小供电电压:1.36 V标称供电电压:1.4 V
表面贴装:YES技术:CMOS
温度等级:OTHER端子形式:BALL
端子节距:0.8 mm端子位置:BOTTOM
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:23 mm
uPs/uCs/外围集成电路类型:DIGITAL SIGNAL PROCESSOR, OTHERBase Number Matches:1

TMS32C6416CGLZ6E3 数据手册

 浏览型号TMS32C6416CGLZ6E3的Datasheet PDF文件第2页浏览型号TMS32C6416CGLZ6E3的Datasheet PDF文件第3页浏览型号TMS32C6416CGLZ6E3的Datasheet PDF文件第4页浏览型号TMS32C6416CGLZ6E3的Datasheet PDF文件第5页浏览型号TMS32C6416CGLZ6E3的Datasheet PDF文件第6页浏览型号TMS32C6416CGLZ6E3的Datasheet PDF文件第7页 
TMS320C6414, TMS320C6415, TMS320C6416  
FIXED-POINT DIGITAL SIGNAL PROCESSORS  
SPRS146K FEBRUARY 2001 REVISED MARCH 2004  
Highest-Performance Fixed-Point Digital  
Signal Processors (DSPs)  
2-, 1.67-, 1.39-ns Instruction Cycle Time  
500-, 600-, 720-MHz Clock Rate  
Eight 32-Bit Instructions/Cycle  
Twenty-Eight Operations/Cycle  
4000, 4800, 5760 MIPS  
Two External Memory Interfaces (EMIFs)  
One 64-Bit (EMIFA), One 16-Bit (EMIFB)  
Glueless Interface to Asynchronous  
Memories (SRAM and EPROM) and  
Synchronous Memories (SDRAM,  
SBSRAM, ZBT SRAM, and FIFO)  
1280M-Byte Total Addressable External  
Memory Space  
Fully Software-Compatible With C62x  
C6414/15/16 Devices Pin-Compatible  
Enhanced Direct-Memory-Access (EDMA)  
Controller (64 Independent Channels)  
VelociTI.2Extensions to VelociTI  
Advanced Very-Long-Instruction-Word  
(VLIW) TMS320C64xDSP Core  
Eight Highly Independent Functional  
Units With VelociTI.2Extensions:  
Six ALUs (32-/40-Bit), Each Supports  
Single 32-Bit, Dual 16-Bit, or Quad  
8-Bit Arithmetic per Clock Cycle  
Two Multipliers Support  
Host-Port Interface (HPI)  
User-Configurable Bus Width (32-/16-Bit)  
32-Bit/33-MHz, 3.3-V PCI Master/Slave  
Interface Conforms to PCI Specification 2.2  
[C6415/C6416 ]  
Three PCI Bus Address Registers:  
Prefetchable Memory  
Non-Prefetchable Memory I/O  
Four-Wire Serial EEPROM Interface  
PCI Interrupt Request Under DSP  
Program Control  
Four 16 x 16-Bit Multiplies  
(32-Bit Results) per Clock Cycle or  
Eight 8 x 8-Bit Multiplies  
(16-Bit Results) per Clock Cycle  
Non-Aligned Load-Store Architecture  
64 32-Bit General-Purpose Registers  
Instruction Packing Reduces Code Size  
All Instructions Conditional  
DSP Interrupt Via PCI I/O Cycle  
Three Multichannel Buffered Serial Ports  
Direct Interface to T1/E1, MVIP, SCSA  
Framers  
Up to 256 Channels Each  
Instruction Set Features  
Byte-Addressable (8-/16-/32-/64-Bit Data)  
8-Bit Overflow Protection  
Bit-Field Extract, Set, Clear  
Normalization, Saturation, Bit-Counting  
VelociTI.2Increased Orthogonality  
Viterbi Decoder Coprocessor (VCP) [C6416]  
Supports Over 500 7.95-Kbps AMR  
Programmable Code Parameters  
ST-Bus-Switching-, AC97-Compatible  
Serial Peripheral Interface (SPI)  
Compatible (Motorola)  
Three 32-Bit General-Purpose Timers  
Universal Test and Operations PHY  
Interface for ATM (UTOPIA) [C6415/C6416]  
UTOPIA Level 2 Slave ATM Controller  
8-Bit Transmit and Receive Operations  
up to 50 MHz per Direction  
Turbo Decoder Coprocessor (TCP) [C6416]  
Supports up to Six 2-Mbps 3GPP  
(6 Iterations)  
Programmable Turbo Code and  
Decoding Parameters  
User-Defined Cell Format up to 64 Bytes  
Sixteen General-Purpose I/O (GPIO) Pins  
Flexible PLL Clock Generator  
IEEE-1149.1 (JTAG )  
L1/L2 Memory Architecture  
128K-Bit (16K-Byte) L1P Program Cache  
(Direct Mapped)  
128K-Bit (16K-Byte) L1D Data Cache  
(2-Way Set-Associative)  
8M-Bit (1024K-Byte) L2 Unified Mapped  
RAM/Cache (Flexible Allocation)  
Boundary-Scan-Compatible  
532-Pin Ball Grid Array (BGA) Package  
(GLZ and ZLZ Suffix), 0.8-mm Ball Pitch  
0.13-µm/6-Level Cu Metal Process (CMOS)  
3.3-V I/Os, 1.2-V/1.25-V Internal (500 MHz)  
3.3-V I/Os, 1.4-V Internal (600 and 720 MHz)  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
C62x, VelociTI.2, VelociTI, and TMS320C64x are trademarks of Texas Instruments.  
Motorola is a trademark of Motorola, Inc.  
IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.  
This document contains information on products in more than one phase  
of development. The status of each device is indicated on the page(s)  
specifying its electrical characteristics.  
Copyright 20034 Texas Instruments Incorporated  
1
POST OFFICE BOX 1443 HOUSTON, TEXAS 772511443  

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