T MS3 20 VC 54 9
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P RO C ES S O R
SPRS078F – SEPTEMBER 1998 – REVISED MAY 2000
D
D
D
Advanced Multibus Architecture With Three
Separate 16-Bit Data Memory Buses and
One Program Memory Bus
D
D
D
D
Arithmetic Instructions With Parallel Store
and Parallel Load
Conditional Store Instructions
Fast Return From Interrupt
40-Bit Arithmetic Logic Unit (ALU)
Including a 40-Bit Barrel Shifter and Two
Independent 40-Bit Accumulators
On-Chip Peripherals
– Software-Programmable Wait-State
Generator and Programmable Bank
Switching
– On-Chip Phase-Locked Loop (PLL) Clock
Generator With Internal Oscillator or
External Clock Source
– Time-Division Multiplexed (TDM) Serial
Port
– Buffered Serial Port (BSP)
– 8-Bit Parallel Host Port Interface (HPI)
– One 16-Bit Timer
17- × 17-Bit Parallel Multiplier Coupled to a
40-Bit Dedicated Adder for Non-Pipelined
Single-Cycle Multiply/Accumulate (MAC)
Operation
D
D
D
Compare, Select, and Store Unit (CSSU) for
the Add/Compare Selection of the Viterbi
Operator
Exponent Encoder to Compute an
Exponent Value of a 40-Bit Accumulator
Value in a Single Cycle
– External-Input/Output (XIO) Off Control
to Disable the External Data Bus,
Address Bus and Control Signals
Two Address Generators With Eight
Auxiliary Registers and Two Auxiliary
Register Arithmetic Units (ARAUs)
D
Power Consumption Control With IDLE1,
IDLE2, and IDLE3 Instructions With
Power-Down Modes
D
D
D
Data Bus With a Bus Holder Feature
Address Bus With a Bus Holder Feature
Extended Addressing Mode for 8M × 16-Bit
Maximum Addressable External Program
Space
D
D
CLKOUT Off Control to Disable CLKOUT
On-Chip Scan-Based Emulation Logic,
†
IEEE Std 1149.1 (JTAG) Boundary Scan
D
D
D
D
D
D
D
D
192K × 16-Bit Maximum Addressable
Memory Space (64K Words Program,
64K Words Data, and 64K Words I/O)
Logic
D
D
D
D
12.5-ns Single-Cycle Fixed-Point
Instruction Execution Time (80 MIPS) for
3.3-V Power Supply)
On-Chip ROM with Some Configurable to
Program/Data Memory
10-ns Single-Cycle Fixed-Point Instruction
Execution Time (100 MIPS) for 3.3-V Power
Supply (2.5-V Core)
Dual-Access On-Chip RAM
Single-Access On-Chip RAM
Single-Instruction Repeat and
Block-Repeat Operations for Program Code
8.3-ns Single-Cycle Fixed-Point Instruction
Execution Time (120 MIPS) for 3.3-V Power
Supply (2.5-V Core) (Product Preview Data)
Block-Memory-Move Instructions for Better
Program and Data Management
Available in a 144-Pin Plastic Thin Quad
Flatpack (TQFP) (PGE Suffix) and a 144-Pin
Ball Grid Array (BGA) (GGU Suffix)
Instructions With a 32-Bit Long Word
Operand
Instructions With Two- or Three-Operand
Reads
NOTE: The data provided in this data sheet for the 8.3-ns, 120 MIPS device is considered to be
Product Preview data as the devices have not completed reliability performance qualification
testing according to TI Quality Systems Specifications.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
†
IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.
Copyright 2000, Texas Instruments Incorporated
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