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TMS320VC549PGE-80 PDF预览

TMS320VC549PGE-80

更新时间： 2024-10-25 23:36:31
品牌 Logo 应用领域
德州仪器 - TI 微控制器和处理器外围集成电路数字信号处理器时钟
页数 文件大小 规格书
60页 785K
描述
IC-SMD-DSP PROCESSOR

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TMS320VC549PGE-80 技术参数

是否Rohs认证：符合生命周期：Obsolete
零件包装代码：QFP包装说明：LQFP-144
针数：144Reach Compliance Code：compliant
HTS代码：8542.31.00.01风险等级：5.8
Is Samacsys：N其他特性：ALSO REQUIRES 3.3V SUPPLY
地址总线宽度：23桶式移位器：YES
位大小：16边界扫描：YES
最大时钟频率：20 MHz外部数据总线宽度：16
格式：FIXED POINT内部总线架构：MULTIPLE
JESD-30 代码：S-PQFP-G144JESD-609代码：e4
长度：20 mm低功率模式：YES
湿度敏感等级：1端子数量：144
最高工作温度：100 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装代码：LFQFP
封装等效代码：QFP144,.87SQ,20封装形状：SQUARE
封装形式：FLATPACK, LOW PROFILE, FINE PITCH峰值回流温度（摄氏度）：260
电源：2.5,3.3 V认证状态：Not Qualified
RAM（字数）：65536座面最大高度：1.6 mm
子类别：Digital Signal Processors最大供电电压：2.75 V
最小供电电压：2.4 V标称供电电压：2.5 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：GULL WING端子节距：0.5 mm
端子位置：QUAD处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：20 mmuPs/uCs/外围集成电路类型：DIGITAL SIGNAL PROCESSOR, OTHER
Base Number Matches：1

TMS320VC549PGE-80 数据手册

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SPRS078F – SEPTEMBER 1998 – REVISED MAY 2000  
D
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Advanced Multibus Architecture With Three  
Separate 16-Bit Data Memory Buses and  
One Program Memory Bus  
D
D
D
D
Arithmetic Instructions With Parallel Store  
and Parallel Load  
Conditional Store Instructions  
Fast Return From Interrupt  
40-Bit Arithmetic Logic Unit (ALU)  
Including a 40-Bit Barrel Shifter and Two  
Independent 40-Bit Accumulators  
On-Chip Peripherals  
– Software-Programmable Wait-State  
Generator and Programmable Bank  
Switching  
– On-Chip Phase-Locked Loop (PLL) Clock  
Generator With Internal Oscillator or  
External Clock Source  
– Time-Division Multiplexed (TDM) Serial  
Port  
– Buffered Serial Port (BSP)  
– 8-Bit Parallel Host Port Interface (HPI)  
– One 16-Bit Timer  
17- × 17-Bit Parallel Multiplier Coupled to a  
40-Bit Dedicated Adder for Non-Pipelined  
Single-Cycle Multiply/Accumulate (MAC)  
Operation  
D
D
D
Compare, Select, and Store Unit (CSSU) for  
the Add/Compare Selection of the Viterbi  
Operator  
Exponent Encoder to Compute an  
Exponent Value of a 40-Bit Accumulator  
Value in a Single Cycle  
– External-Input/Output (XIO) Off Control  
to Disable the External Data Bus,  
Address Bus and Control Signals  
Two Address Generators With Eight  
Auxiliary Registers and Two Auxiliary  
Register Arithmetic Units (ARAUs)  
D
Power Consumption Control With IDLE1,  
IDLE2, and IDLE3 Instructions With  
Power-Down Modes  
D
D
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Data Bus With a Bus Holder Feature  
Address Bus With a Bus Holder Feature  
Extended Addressing Mode for 8M × 16-Bit  
Maximum Addressable External Program  
Space  
D
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CLKOUT Off Control to Disable CLKOUT  
On-Chip Scan-Based Emulation Logic,  
†
IEEE Std 1149.1 (JTAG) Boundary Scan  
D
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192K × 16-Bit Maximum Addressable  
Memory Space (64K Words Program,  
64K Words Data, and 64K Words I/O)  
Logic  
D
D
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12.5-ns Single-Cycle Fixed-Point  
Instruction Execution Time (80 MIPS) for  
3.3-V Power Supply)  
On-Chip ROM with Some Configurable to  
Program/Data Memory  
10-ns Single-Cycle Fixed-Point Instruction  
Execution Time (100 MIPS) for 3.3-V Power  
Supply (2.5-V Core)  
Dual-Access On-Chip RAM  
Single-Access On-Chip RAM  
Single-Instruction Repeat and  
Block-Repeat Operations for Program Code  
8.3-ns Single-Cycle Fixed-Point Instruction  
Execution Time (120 MIPS) for 3.3-V Power  
Supply (2.5-V Core) (Product Preview Data)  
Block-Memory-Move Instructions for Better  
Program and Data Management  
Available in a 144-Pin Plastic Thin Quad  
Flatpack (TQFP) (PGE Suffix) and a 144-Pin  
Ball Grid Array (BGA) (GGU Suffix)  
Instructions With a 32-Bit Long Word  
Operand  
Instructions With Two- or Three-Operand  
Reads  
NOTE: The data provided in this data sheet for the 8.3-ns, 120 MIPS device is considered to be  
Product Preview data as the devices have not completed reliability performance qualification  
testing according to TI Quality Systems Specifications.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
†
IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.  
Copyright 2000, Texas Instruments Incorporated  
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POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443  
1234567...60

中文翻译

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TMS320VC549PGE-80 替代型号

型号 品牌 替代类型 描述 数据表
TMS320VC549PGER-80 TI

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