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TMS320P25PHL PDF预览

TMS320P25PHL

更新时间： 2024-10-27 13:14:51
品牌 Logo 应用领域
德州仪器 - TI 数字信号处理器
页数 文件大小 规格书
48页 764K
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TMS320P25PHL 数据手册

 浏览型号TMS320P25PHL的Datasheet PDF文件第2页浏览型号TMS320P25PHL的Datasheet PDF文件第3页浏览型号TMS320P25PHL的Datasheet PDF文件第4页浏览型号TMS320P25PHL的Datasheet PDF文件第5页浏览型号TMS320P25PHL的Datasheet PDF文件第6页浏览型号TMS320P25PHL的Datasheet PDF文件第7页 
TMS320P25  
DIGITAL SIGNAL PROCESSOR  
SPRS028 – OCTOBER 1994  
FN PACKAGE  
(TOP VIEW)  
• Instruction Cycle Time of 100 ns (40 MHz)  
• 4K Words of On-Chip Secure Program  
EPROM  
• 544 Words of On-Chip Data RAM  
• 128K Words of Data/Program Space  
• 16 Parallel I/O Ports  
• 32-Bit ALU/Accumulator  
• 16 × 16-Bit Multiplier With a 32-Bit Product  
9
8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61  
V
IACK  
MSC  
60  
59  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
SS  
D7  
D6  
D5  
58 CLKOUT1  
57  
CLKOUT2  
D4  
D3  
D2  
D1  
D0  
56 XF  
55  
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
44  
HOLDA  
DX  
FSX  
X2 CLKIN  
X1  
• Block Moves for Data/Program  
Management  
SYNC  
INT0  
INT1  
INT2  
• Repeat Instructions for Efficient Use of  
BR  
Program Space  
STRB  
R/W  
PS  
IS  
DS  
• Serial Port for Direct Codec Interface  
V
DR  
CC  
• Synchronization Input for Synchronous  
FSR  
Multiprocessor Configurations  
A0 26  
V
SS  
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43  
• Wait States for Communication to Slow  
Off-Chip Memories/Peripherals  
• On-Chip Timer for Control Operations  
• Single 5-V Supply  
PH PACKAGE  
(TOP VIEW)  
• Packaging:  
– 68-Lead Plastic J-Leaded Chip Carrier  
(FN Suffix)  
– 80-Lead Plastic Quad Flatpack  
(PH Suffix)  
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65  
1
64  
63  
62  
61  
60  
59  
58  
57  
56  
55  
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
44  
43  
42  
41  
IACK  
V
V
SS  
SS  
2
V
V
V
CC  
CC  
CC  
• 68-to-28-Lead Conversion Adapter Socket  
3
A15  
A14  
A13  
A12  
for EPROM Programming  
4
5
CLKX  
description  
6
V
SS  
7
CLKR  
RS  
V
SS  
The TMS320P25 digital signal processor is a  
member of the TMS320 family of VLSI digital  
signal processors and peripherals. The TMS320  
family supports a wide range of digital signal  
8
A11  
A10  
A9  
9
READY  
HOLD  
BIO  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
A8  
MP /MC  
D15  
V
processing  
applications,  
such  
as  
image  
CC  
V
CC  
telecommunications,  
modems,  
V
A7  
A6  
SS  
processing, speech processing, spectrum  
analysis, audio processing, digital filtering,  
high-speed control, graphics, and other  
computation intensive applications.  
D14  
D13  
V
SS  
V
A5  
A4  
A3  
A2  
A1  
NC  
V
CC  
D12  
D11  
D10  
D9  
With a 100-ns instruction cycle time and an  
innovative memory configuration, the ’320P25  
performs operations necessary for many real-time  
digital signal processing algorithms. Since most  
instructions require only one cycle, the  
TMS320P25 is capable of executing ten million  
instructions per second. On-chip programmable  
data/program RAM of 544 words of 16 bits,  
on-chip program EPROM of 4K words (one-time  
programmable memory), direct addressing of up  
D8  
V
SS  
SS  
SS  
V
A0  
25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40  
Copyright 1994, Texas Instruments Incorporated  
ADVANCE INFORMATION concerns new products in the sampling or  
preproduction phase of development. Characteristic data and other  
specifications are subject to change without notice.  
1
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443  
1234567...48

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