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TMS320LC542PGE-80 PDF预览

TMS320LC542PGE-80

更新时间： 2024-10-29 05:32:03
品牌 Logo 应用领域
德州仪器 - TI 时钟外围集成电路
页数 文件大小 规格书
113页 1732K
描述
IC 16-BIT, 160 MHz, OTHER DSP, PQFP144, PLASTIC, TQFP-144, Digital Signal Processor

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TMS320LC542PGE-80 技术参数

生命周期：Obsolete零件包装代码：QFP
包装说明：PLASTIC, TQFP-144针数：144
Reach Compliance Code：unknownECCN代码：3A001.A.3
HTS代码：8542.31.00.01风险等级：5.72
Is Samacsys：N地址总线宽度：23
桶式移位器：YES边界扫描：YES
最大时钟频率：160 MHz外部数据总线宽度：16
格式：FIXED POINT内部总线架构：MULTIPLE
JESD-30 代码：S-PQFP-G144长度：20 mm
低功率模式：YES端子数量：144
封装主体材料：PLASTIC/EPOXY封装代码：LFQFP
封装形状：SQUARE封装形式：FLATPACK, LOW PROFILE, FINE PITCH
认证状态：Not Qualified座面最大高度：1.6 mm
最大供电电压：3.6 V最小供电电压：3 V
标称供电电压：3.3 V表面贴装：YES
技术：CMOS端子形式：GULL WING
端子节距：0.5 mm端子位置：QUAD
宽度：20 mmuPs/uCs/外围集成电路类型：DIGITAL SIGNAL PROCESSOR, OTHER
Base Number Matches：1

TMS320LC542PGE-80 数据手册

 浏览型号TMS320LC542PGE-80的Datasheet PDF文件第2页浏览型号TMS320LC542PGE-80的Datasheet PDF文件第3页浏览型号TMS320LC542PGE-80的Datasheet PDF文件第4页浏览型号TMS320LC542PGE-80的Datasheet PDF文件第5页浏览型号TMS320LC542PGE-80的Datasheet PDF文件第6页浏览型号TMS320LC542PGE-80的Datasheet PDF文件第7页 
TMS320C54x, TMS320LC54x, TMS320VC54x  
FIXED-POINT DIGITAL SIGNAL PROCESSORS  
SPRS039B – FEBRUARY 1996 – REVISED FEBRUARY 1998  
Advanced Multibus Architecture With Three  
Separate 16-Bit Data Memory Buses and  
One Program Memory Bus  
Fast Return From Interrupt  
On-Chip Peripherals  
– Software-Programmable Wait-State  
Generator and Programmable Bank  
Switching  
– On-Chip Phase-Locked Loop (PLL) Clock  
Generator With Internal Oscillator or  
External Clock Source  
– Full-Duplex Serial Port to Support 8- or  
16-Bit Transfers (’541, ’LC545, and  
’LC546 Only)  
– Time-Division Multiplexed (TDM) Serial  
Port (’542, ’543, ’548, and ’549 Only)  
– Buffered Serial Port (BSP) (’542, ’543,  
’LC545, ’LC546, ’548, and ’549 Only)  
– 8-Bit Parallel Host Port Interface (HPI)  
(’542, ’LC545, ’548, and ’549)  
40-Bit Arithmetic Logic Unit (ALU)  
Including a 40-Bit Barrel Shifter and Two  
Independent 40-Bit Accumulators  
17- × 17-Bit Parallel Multiplier Coupled to a  
40-Bit Dedicated Adder for Non-Pipelined  
Single-Cycle Multiply/Accumulate (MAC)  
Operation  
Compare, Select, and Store Unit (CSSU) for  
the Add/Compare Selection of the Viterbi  
Operator  
Exponent Encoder to Compute an  
Exponent Value of a 40-Bit Accumulator  
Value in a Single Cycle  
Two Address Generators With Eight  
Auxiliary Registers and Two Auxiliary  
Register Arithmetic Units (ARAUs)  
– One 16-Bit Timer  
– External-Input/Output (XIO) Off Control  
to Disable the External Data Bus,  
Address Bus and Control Signals  
Data Bus With a Bus Holder Feature  
Power Consumption Control With IDLE1,  
IDLE2, and IDLE3 Instructions With  
Power-Down Modes  
Address Bus With a Bus Holder Feature  
(’548 and ’549 Only)  
Extended Addressing Mode for 8M × 16-Bit  
Maximum Addressable External Program  
Space (’548 and ’549 Only)  
CLKOUT Off Control to Disable CLKOUT  
On-Chip Scan-Based Emulation Logic,  
†
IEEE Std 1149.1 (JTAG) Boundary Scan  
192K × 16-Bit Maximum Addressable  
Memory Space (64K Words Program,  
64K Words Data, and 64K Words I/O)  
Logic  
25-ns Single-Cycle Fixed-Point Instruction  
Execution Time [40 MIPS] for 5-V Power  
Supply (’C541 and ’C542 Only)  
On-Chip ROM with Some Configurable to  
Program/Data Memory  
20-ns and 25-ns Single-Cycle Fixed-Point  
Instruction Execution Time (50 MIPS and  
40 MIPS) for 3.3-V Power Supply (’LC54x)  
Dual-Access On-Chip RAM  
Single-Access On-Chip RAM (’548/’549)  
Single-Instruction Repeat and  
Block-Repeat Operations for Program Code  
15-ns Single-Cycle Fixed-Point Instruction  
Execution Time (66 MIPS) for 3.3-V Power  
Supply (’LC54xA, ’548, ’LC549)  
Block-Memory-Move Instructions for Better  
Program and Data Management  
12.5-ns Single-Cycle Fixed-Point  
Instruction Execution Time (80 MIPS) for  
3.3-V Power Supply (’LC549)  
Instructions With a 32-Bit Long Word  
Operand  
Instructions With Two- or Three-Operand  
Reads  
10-ns Single-Cycle Fixed-Point Instruction  
Execution Time (100 MIPS) for 3.3-V Power  
Supply (2.5-V Core) (’VC549)  
Arithmetic Instructions With Parallel Store  
and Parallel Load  
Conditional Store Instructions  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
†
IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.  
Copyright 1998, Texas Instruments Incorporated  
UNLESS OTHERWISE NOTED this document contains ADVANCE  
INFORMATION on new products in the sampling or preproduction phase  
of development. Characteristic data and other specifications are subject  
to change without notice.  
1
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443  
1234567...113

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