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TMS320LC545APBK-66 PDF预览

TMS320LC545APBK-66

更新时间： 2024-10-29 02:58:31
品牌 Logo 应用领域
德州仪器 - TI 时钟外围集成电路
页数 文件大小 规格书
63页 864K
描述
FIXED-POINT DIGITAL SIGNAL PROCESSORS

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中文翻译

获取价格

TMS320LC545APBK-66 技术参数

是否无铅： 含铅生命周期：Obsolete
零件包装代码：QFP包装说明：LFQFP,
针数：128Reach Compliance Code：unknown
HTS代码：8542.31.00.01Factory Lead Time：1 week
风险等级：5.82地址总线宽度：16
桶式移位器：YES边界扫描：YES
最大时钟频率：20 MHz外部数据总线宽度：16
格式：FIXED POINT内部总线架构：MULTIPLE
JESD-30 代码：S-PQFP-G128长度：14 mm
低功率模式：YES端子数量：128
封装主体材料：PLASTIC/EPOXY封装代码：LFQFP
封装形状：SQUARE封装形式：FLATPACK, LOW PROFILE, FINE PITCH
认证状态：Not Qualified座面最大高度：1.6 mm
最大供电电压：3.6 V最小供电电压：3 V
标称供电电压：3.3 V表面贴装：YES
技术：CMOS端子形式：GULL WING
端子节距：0.4 mm端子位置：QUAD
宽度：14 mmuPs/uCs/外围集成电路类型：DIGITAL SIGNAL PROCESSOR, OTHER
Base Number Matches：1

TMS320LC545APBK-66 数据手册

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SPRS078G − SEPTEMBER 1998 − REVISED OCTOBER 2004  
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Advanced Multibus Architecture With Three  
Separate 16-Bit Data Memory Buses and  
One Program Memory Bus  
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Arithmetic Instructions With Parallel Store  
and Parallel Load  
Conditional Store Instructions  
Fast Return From Interrupt  
40-Bit Arithmetic Logic Unit (ALU)  
Including a 40-Bit Barrel Shifter and Two  
Independent 40-Bit Accumulators  
On-Chip Peripherals  
− Software-Programmable Wait-State  
Generator and Programmable Bank  
Switching  
− On-Chip Phase-Locked Loop (PLL) Clock  
Generator With Internal Oscillator or  
External Clock Source  
− Time-Division Multiplexed (TDM) Serial  
Port  
− Buffered Serial Port (BSP)  
− 8-Bit Parallel Host Port Interface (HPI)  
− One 16-Bit Timer  
17- × 17-Bit Parallel Multiplier Coupled to a  
40-Bit Dedicated Adder for Non-Pipelined  
Single-Cycle Multiply/Accumulate (MAC)  
Operation  
D
D
D
Compare, Select, and Store Unit (CSSU) for  
the Add/Compare Selection of the Viterbi  
Operator  
Exponent Encoder to Compute an  
Exponent Value of a 40-Bit Accumulator  
Value in a Single Cycle  
− External-Input/Output (XIO) Off Control  
to Disable the External Data Bus,  
Address Bus and Control Signals  
Two Address Generators With Eight  
Auxiliary Registers and Two Auxiliary  
Register Arithmetic Units (ARAUs)  
D
Power Consumption Control With IDLE1,  
IDLE2, and IDLE3 Instructions With  
Power-Down Modes  
D
D
D
Data Bus With a Bus Holder Feature  
Address Bus With a Bus Holder Feature  
Extended Addressing Mode for 8M × 16-Bit  
Maximum Addressable External Program  
Space  
D
D
CLKOUT Off Control to Disable CLKOUT  
On-Chip Scan-Based Emulation Logic,  
†
IEEE Std 1149.1 (JTAG) Boundary Scan  
D
D
D
D
D
D
D
D
192K × 16-Bit Maximum Addressable  
Memory Space (64K Words Program,  
64K Words Data, and 64K Words I/O)  
Logic  
D
D
D
D
12.5-ns Single-Cycle Fixed-Point  
Instruction Execution Time (80 MIPS) for  
3.3-V Power Supply)  
On-Chip ROM with Some Configurable to  
Program/Data Memory  
10-ns Single-Cycle Fixed-Point Instruction  
Execution Time (100 MIPS) for 3.3-V Power  
Supply (2.5-V Core)  
Dual-Access On-Chip RAM  
Single-Access On-Chip RAM  
Single-Instruction Repeat and  
Block-Repeat Operations for Program Code  
8.3-ns Single-Cycle Fixed-Point Instruction  
Execution Time (120 MIPS) for 3.3-V Power  
Supply (2.5-V Core)  
Block-Memory-Move Instructions for Better  
Program and Data Management  
Available in a 144-Pin Plastic Thin Quad  
Flatpack (TQFP) (PGE Suffix) and a 144-Pin  
Ball Grid Array (BGA) (GGU Suffix)  
Instructions With a 32-Bit Long Word  
Operand  
Instructions With Two- or Three-Operand  
Reads  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor s and disclaimers thereto appears at the end of this data sheet.  
†
IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.  
All trademarks are the property of their respective owners.  
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Copyright 2004, Texas Instruments Incorporated  
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1
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443  
 
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中文翻译

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