T
M
S
S
3
3
2
2
0
0
L
L
C
F
2
2
4
4
0
0
6
7
A
A
,
,
T
M
S
S
3
3
2
2
0
0
L
L
C
F
2
2
4
4
0
D
0
4
S
6
A
P
A
,
,
T MS 32 0L F24 02 A
T MS 32 0L C2 40 2A
CO N TR OL LE RS
T
M
T
M
SPRS145B – JULY 2000 – REVISED DECEMBER 2000
D
D
High-Performance Static CMOS Technology
– 25-ns Instruction Cycle Time (40 MHz)
– 40-MIPS Performance
D
External Memory Interface (LF2407A)
– 192K Words x 16 Bits of Total Memory:
64K Program, 64K Data, 64K I/O
– Low-Power 3.3-V Design
D
D
Watchdog (WD) Timer Module
Based on TMS320C2xx DSP CPU Core
– Code-Compatible With F243/F241/C242
– Instruction Set and Module Compatible
With F240/C240
10-Bit Analog-to-Digital Converter (ADC)
– 8 or 16 Multiplexed Input Channels
– 500 ns Minimum Conversion Time
– Selectable Twin 8-Input Sequencers
Triggered by Two Event Managers
D
D
Flash (LF) and ROM (LC) Device Options
†
†
– LF240xA : LF2407A, LF2406A, LF2402A
D
D
D
D
D
D
D
Controller Area Network (CAN) 2.0B Module
Serial Communications Interface (SCI)
16-Bit Serial Peripheral Interface (SPI)
– LC240xA : LC2406A, LC2404A, LC2402A
On-Chip Memory
– Up to 32K Words x 16 Bits of Flash
EEPROM (4 Sectors) or ROM
– Programmable “Code-Security” Feature
for the On-Chip Flash/ROM
– Up to 2.5K Words x 16 Bits of
Data/Program RAM
Phase-Locked-Loop (PLL)-Based Clock
Generation
Up to 40 Individually Programmable,
Multiplexed General-Purpose Input/Output
(GPIO) Pins
– 544 Words of Dual-Access RAM
– Up to 2K Words of Single-Access RAM
Five External Interrupts (Power Drive
Protection, Reset, and Two Maskable
Interrupts)
D
D
Boot ROM (LF240xA Devices)
– SCI/SPI Bootloader
Power Management:
Two Event-Manager (EV) Modules
(EVA and EVB), Each Include:
– Two 16-Bit General-Purpose Timers
– Eight 16-Bit Pulse-Width Modulation
(PWM) Channels Which Enable:
– Three-Phase Inverter Control
– Center- or Edge-Alignment of PWM
Channels
– Emergency PWM Channel Shutdown
With External PDPINTx Pin
– Programmable Deadband (Deadtime)
Prevents Shoot-Through Faults
– Three Capture Units For Time-Stamping
of External Events
– Three Power-Down Modes
– Ability to Power Down Each Peripheral
Independently
D
D
Real-Time JTAG-Compliant Scan-Based
‡
Emulation, IEEE Standard 1149.1 (JTAG)
Development Tools Include:
– Texas Instruments (TI) ANSI C Compiler,
Assembler/Linker, and Code Composer
Studio Debugger
– Evaluation Modules
– Scan-Based Self-Emulation (XDS510 )
– Broad Third-Party Digital Motor Control
Support
– Input Qualifier for Select Pins
– On-Chip Position Encoder Interface
Circuitry
– Synchronized A-to-D Conversion
– Designed for AC Induction, BLDC,
Switched Reluctance, and Stepper Motor
Control
D
D
Package Options
– 144-Pin LQFP PGE (LF2407A)
– 100-Pin LQFP PZ (LC2404A, LC2406A,
LF2406A)
– 64-Pin QFP PG (LC2402A and LF2402A)
Extended Temperature Options (A and S)
– A: – 40°C to 85°C
– S: – 40°C to 125°C
– Applicable for Multiple Motor and/or
Converter Control
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
7
Code Composer Studio and XDS510 are trademarks of Texas Instruments.
†
‡
Throughout this data sheet, 240xA is used as a generic name for the LF240xA/LC240xA generation of devices.
IEEE Standard 1149.1–1990, IEEE Standard Test-Access Port
Copyright 2000, Texas Instruments Incorporated
A
D
e
e
V
p
c
A
N
d
C
u
a
E
c
I
n
s
N
F
O
p
r
R
h
e
M
A
e
s
T
I
O
N
o
c
d
o
e
n
v
c
e
e
l
c
r
o
n
p
h
s
m
a
n
e
.
w
p
r
o
d
c
u
t
c
t
s
i
c
n
t
a
h
e
s
a
a
n
m
d
p
l
i
n
g
oth er
o
r
p
r
r
o
t
o
i
n
o
a
s
f
e
n
t
C
h
a
r
a
er
not ice .
i
s
t
i
d
t
a
s
p
i
f
i
c
t
i
a
u
b
j
e
c
t
t
o
n
g
e
w
i
t
h
o
u
t
1
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
5秒后页面跳转
三星深化印度制造布局，供应链本地化进程加速
芯擎科技“星辰一号”自动驾驶芯片点亮成功，2025年量产在即
纳微科技震撼发布GaNSlim革新氮化镓功率芯片
意法半导体发布第四代SiC技术，助力电动汽车电驱
微信公众号
抖音公众号
浙公网安备 33010502006866号 浙ICP备10014259号-119
营业执照ICP证
数据手册
如果您发现信息不准确，
