TMS320DM6437
Digital Media Processor
SPRS345D–NOVEMBER 2006–REVISED JUNE 2008
www.ti.com
Contents
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TMS320DM6437 Digital Media Processor........... 1
6
Peripheral Information and Electrical
Specifications ......................................... 162
1.1 Features .............................................. 1
1.2 Description............................................ 3
1.3 Functional Block Diagram ............................ 5
6.1 Parameter Information ............................. 162
6.2
Recommended Clock and Control Signal Transition
Behavior............................................ 163
Revision History............................................... 7
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6.3 Power Supplies .................................... 163
Device Overview ......................................... 8
2.1 Device Characteristics................................ 8
2.2 CPU (DSP Core) Description......................... 9
2.3 C64x+ CPU.......................................... 12
2.4 Memory Map Summary ............................. 13
2.5 Pin Assignments .................................... 17
2.6 Terminal Functions.................................. 25
2.7 Device Support ...................................... 70
6.4
Enhanced Direct Memory Access (EDMA3)
Controller........................................... 170
6.5 Reset............................................... 183
6.6
External Clock Input From MXI/CLKIN Pin ........ 192
6.7 Clock PLLs......................................... 194
6.8 Interrupts........................................... 200
6.9 External Memory Interface (EMIF)................. 203
6.10 Video Processing Sub-System (VPSS) Overview . 211
6.11 Universal Asynchronous Receiver/Transmitter
(UART) ............................................. 234
2.8
Device and Development-Support Tool
Nomenclature ....................................... 70
2.9 Documentation Support ............................. 72
Device Configurations................................. 73
3.1 System Module Registers ........................... 73
3.2 Power Considerations............................... 74
3.3 Clock Considerations................................ 77
3.4 Boot Sequence...................................... 80
3.5 Configurations At Reset ............................. 92
3.6 Configurations After Reset .......................... 95
3.7 Multiplexed Pin Configurations...................... 99
6.12 Inter-Integrated Circuit (I2C) ....................... 237
6.13 Host-Port Interface (HPI) Peripheral............... 241
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6.14 Multichannel Buffered Serial Port (McBSP)........ 246
6.15 Multichannel Audio Serial Port (McASP0)
Peripheral .......................................... 256
6.16 High-End Controller Area Network Controller
(HECC)............................................. 264
6.17 Ethernet Media Access Controller (EMAC) ........ 270
6.18 Management Data Input/Output (MDIO) .......... 277
6.19 Timers.............................................. 278
6.20 Peripheral Component Interconnect (PCI)......... 281
6.21 Pulse Width Modulator (PWM)..................... 287
6.22 VLYNQ ............................................. 289
6.23 General-Purpose Input/Output (GPIO)............. 293
6.24 IEEE 1149.1 JTAG................................. 297
Mechanical Data....................................... 299
7.1 Thermal Data for ZWT ............................. 299
7.1.1 Thermal Data for ZDU............................. 300
7.1.2 Packaging Information............................. 300
3.8
Device Initialization Sequence After Reset ........ 152
3.9 Debugging Considerations......................... 154
System Interconnect ................................. 156
4.1 System Interconnect Block Diagram............... 156
Device Operating Conditions....................... 158
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5.1
Absolute Maximum Ratings Over Operating
7
Temperature Range (Unless Otherwise Noted) ... 158
5.2 Recommended Operating Conditions ............. 159
5.3
Electrical Characteristics Over Recommended
Ranges of Supply Voltage and Operating
Temperature (Unless Otherwise Noted) ........... 160
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Contents
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