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TMS320C6748BZCEA3E PDF预览

TMS320C6748BZCEA3E

更新时间: 2024-10-29 12:04:47
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德州仪器 - TI /
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273页 1954K
描述
TMS320C6748 Fixed- and Floating-Point DSP

TMS320C6748BZCEA3E 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:BGA包装说明:LFBGA, BGA361,19X19,25
针数:361Reach Compliance Code:compliant
ECCN代码:3A001.A.3HTS代码:8542.31.00.01
风险等级:5.59地址总线宽度:23
桶式移位器:NO位大小:32
边界扫描:YES最大时钟频率:50 MHz
外部数据总线宽度:16格式:FLOATING POINT
内部总线架构:MULTIPLEJESD-30 代码:S-PBGA-B361
JESD-609代码:e1长度:13 mm
低功率模式:YES湿度敏感等级:3
端子数量:361最高工作温度:105 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:LFBGA封装等效代码:BGA361,19X19,25
封装形状:SQUARE封装形式:GRID ARRAY, LOW PROFILE, FINE PITCH
峰值回流温度(摄氏度):260电源:1.2,1.8,3.3 V
认证状态:Not QualifiedRAM(字数):8192
座面最大高度:1.3 mm子类别:Digital Signal Processors
最大供电电压:1.35 V最小供电电压:0.95 V
标称供电电压:1 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Tin/Silver/Copper (Sn/Ag/Cu)端子形式:BALL
端子节距:0.65 mm端子位置:BOTTOM
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:13 mm
uPs/uCs/外围集成电路类型:DIGITAL SIGNAL PROCESSOR, OTHERBase Number Matches:1

TMS320C6748BZCEA3E 数据手册

 浏览型号TMS320C6748BZCEA3E的Datasheet PDF文件第2页浏览型号TMS320C6748BZCEA3E的Datasheet PDF文件第3页浏览型号TMS320C6748BZCEA3E的Datasheet PDF文件第4页浏览型号TMS320C6748BZCEA3E的Datasheet PDF文件第5页浏览型号TMS320C6748BZCEA3E的Datasheet PDF文件第6页浏览型号TMS320C6748BZCEA3E的Datasheet PDF文件第7页 
Sample &  
Buy  
Support &  
Community  
Product  
Folder  
Tools &  
Software  
Technical  
Documents  
TMS320C6748  
www.ti.com  
SPRS590E JUNE 2009REVISED AUGUST 2013  
TMS320C6748™ Fixed- and Floating-Point DSP  
Check for Samples: TMS320C6748  
1 TMS320C6748 Fixed- and Floating-Point DSP  
1.1 Features  
12  
2 SP x SP DP Every Two Clocks  
2 SP x DP DP Every Three Clocks  
2 DP x DP DP Every Four Clocks  
• 375- and 456-MHz C674x™ Fixed- and Floating-  
Point VLIW DSP  
• C674x Instruction Set Features  
– Superset of the C67x+™ and C64x+™ ISAs  
– Up to 3648 MIPS and 2746 MFLOPS  
– Byte-Addressable (8-, 16-, 32-, and 64-Bit  
Data)  
– 8-Bit Overflow Protection  
– Bit-Field Extract, Set, Clear  
Fixed-Point Multiply Supports Two 32 x  
32-Bit Multiplies, Four 16 x 16-Bit  
Multiplies, or Eight 8 x 8-Bit Multiplies per  
Clock Cycle, and Complex Multiples  
– Instruction Packing Reduces Code Size  
– All Instructions Conditional  
– Hardware Support for Modulo Loop  
Operation  
– Protected Mode Operation  
– Exceptions Support for Error Detection and  
Program Redirection  
– Normalization, Saturation, Bit-Counting  
– Compact 16-Bit Instructions  
• C674x Two-Level Cache Memory Architecture  
– 32KB of L1P Program RAM/Cache  
– 32KB of L1D Data RAM/Cache  
– 256KB of L2 Unified Mapped RAM/Cache  
– Flexible RAM/Cache Partition (L1 and L2)  
• Enhanced Direct-Memory-Access Controller 3  
(EDMA3):  
• Software Support  
– TI DSP/BIOS™  
– Chip Support Library and DSP Library  
• 128KB of RAM Shared Memory  
• 1.8-V or 3.3-V LVCMOS I/Os (Except for USB  
and DDR2 Interfaces)  
• Two External Memory Interfaces:  
– EMIFA  
– 2 Channel Controllers  
– 3 Transfer Controllers  
– 64 Independent DMA Channels  
– 16 Quick DMA Channels  
NOR (8- or 16-Bit-Wide Data)  
NAND (8- or 16-Bit-Wide Data)  
16-Bit SDRAM with 128-MB Address  
Space  
– Programmable Transfer Burst Size  
• TMS320C674x™ Floating-Point VLIW DSP Core  
– Load-Store Architecture with Nonaligned  
Support  
– 64 General-Purpose Registers (32 Bit)  
– Six ALU (32- and 40-Bit) Functional Units  
– DDR2/Mobile DDR Memory Controller with  
one of the following:  
16-Bit DDR2 SDRAM with 256-MB  
Address Space  
16-Bit mDDR SDRAM with 256-MB  
Address Space  
Supports 32-Bit Integer, SP (IEEE Single  
Precision/32-Bit) and DP (IEEE Double  
Precision/64-Bit) Floating Point  
Supports up to Four SP Additions Per  
Clock, Four DP Additions Every Two  
Clocks  
Supports up to Two Floating-Point (SP or  
DP) Reciprocal Approximation (RCPxP)  
and Square-Root Reciprocal  
• Three Configurable 16550-Type UART Modules:  
– with Modem Control Signals  
– 16-Byte FIFO  
– 16x or 13x Oversampling Option  
• LCD Controller  
Approximation (RSQRxP) Operations Per  
Cycle  
• Two Serial Peripheral Interfaces (SPIs) Each  
with Multiple Chip Selects  
– Two Multiply Functional Units:  
• Two Multimedia Card (MMC)/Secure Digital (SD)  
Card Interfaces with Secure Data I/O (SDIO)  
Interfaces  
Mixed-Precision IEEE Floating-Point  
Multiply Supported up to:  
2 SP x SP SP Per Clock  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
2
All trademarks are the property of their respective owners.  
PRODUCTION DATA information is current as of publication date. Products conform to  
specifications per the terms of the Texas Instruments standard warranty. Production  
processing does not necessarily include testing of all parameters.  
Copyright © 2009–2013, Texas Instruments Incorporated  
 
 
 

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