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TMS320C6745_13

更新时间： 2024-10-29 12:02:19
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德州仪器 - TI 数字信号处理器
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227页 1918K
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TMS320C6745,TMS320C6747 Fixed/Floating-Point Digital Signal Processor

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TMS320C6745, TMS320C6747  
www.ti.com  
SPRS377E –SEPTEMBER 2008–REVISED FEBRUARY 2013  
TMS320C6745,TMS320C6747 Fixed/Floating-Point Digital Signal Processor  
Check for Samples: TMS320C6745, TMS320C6747  
1 TMS320C6745/6747 Fixed/Floating-Point Digital Signal Processor  
1.1 Features  
123  
(EDMA3):  
• Highlights  
– 2 Transfer Controllers  
– 32 Independent DMA Channels  
– 8 Quick DMA Channels  
– Programmable Transfer Burst Size  
– 375/456-MHz C674x VLIW DSP  
– TMS320C674x Fixed/Floating-Point VLIW  
DSP Core  
– Enhanced Direct-Memory-Access Controller  
3 (EDMA3)  
– 128K-Byte RAM Shared Memory (C6747  
Only)  
• TMS320C674x Fixed/Floating-Point VLIW DSP  
Core  
– Load-Store Architecture With Non-Aligned  
Support  
– Two External Memory Interfaces  
– Three Configurable 16550 type UART  
Modules  
– 64 General-Purpose Registers (32 Bit)  
– Six ALU (32-/40-Bit) Functional Units  
– LCD Controller (C6747 Only)  
•
Supports 32-Bit Integer, SP (IEEE Single  
Precision/32-Bit) and DP (IEEE Double  
Precision/64-Bit) Floating Point  
Supports up to Four SP Additions Per  
Clock, Four DP Additions Every 2 Clocks  
Supports up to Two Floating Point (SP or  
DP) Reciprocal Approximation (RCPxP)  
and Square-Root Reciprocal  
Approximation (RSQRxP) Operations Per  
Cycle  
– Two Serial Peripheral Interfaces (SPI)  
– Multimedia Card (MMC)/Secure Digital (SD)  
– Two Master/Slave Inter-Integrated Circuit  
– One Host-Port Interface (HPI) (C6747 only)  
– USB 1.1 OHCI (Host) With Integrated PHY  
(USB1) (C6747 Only)  
•
•
• Applications  
– Industrial Control  
– USB, Networking  
– High-Speed Encoding  
– Professional Audio  
– Two Multiply Functional Units  
•
Mixed-Precision IEEE Floating Point  
Multiply Supported up to:  
• Software Support  
–
–
–
–
2 SP x SP -> SP Per Clock  
– TI DSP/BIOS™  
2 SP x SP -> DP Every Two Clocks  
2 SP x DP -> DP Every Three Clocks  
2 DP x DP -> DP Every Four Clocks  
– Chip Support Library and DSP Library  
• 375/456-MHz C674x VLIW DSP  
• C674x Instruction Set Features  
– Superset of the C67x+™ and C64x+™ ISAs  
– 3648/2736 C674x MIPS/MFLOPS  
– Byte-Addressable (8-/16-/32-/64-Bit Data)  
– 8-Bit Overflow Protection  
– Bit-Field Extract, Set, Clear  
– Normalization, Saturation, Bit-Counting  
– Compact 16-Bit Instructions  
• C674x Two Level Cache Memory Architecture  
– 32K-Byte L1P Program RAM/Cache  
– 32K-Byte L1D Data RAM/Cache  
– 256K-Byte L2 Unified Mapped RAM/Cache  
– Flexible RAM/Cache Partition (L1 and L2)  
•
Fixed Point Multiply Supports Two 32 x  
32-Bit Multiplies, Four 16 x 16-Bit  
Multiplies, or Eight 8 x 8-Bit Multiplies per  
Clock Cycle, and Complex Multiples  
– Instruction Packing Reduces Code Size  
– All Instructions Conditional  
– Hardware Support for Modulo Loop  
Operation  
– Protected Mode Operation  
– Exceptions Support for Error Detection and  
Program Redirection  
• 128K-Byte RAM Shared Memory (C6747 Only)  
• 3.3V LVCMOS IOs (except for USB interfaces)  
• Two External Memory Interfaces:  
– EMIFA  
• Enhanced Direct-Memory-Access Controller 3  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
DSP/BIOS, PowerPAD, TMS320C6000, C6000 are trademarks of Texas Instruments.  
2
3
All other trademarks are the property of their respective owners.  
PRODUCTION DATA information is current as of publication date. Products conform to  
specifications per the terms of the Texas Instruments standard warranty. Production  
processing does not necessarily include testing of all parameters.  
Copyright © 2008–2013, Texas Instruments Incorporated  
 
 
 
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