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TMS320C6472ECTZA PDF预览

TMS320C6472ECTZA

更新时间: 2024-10-28 12:16:07
品牌 Logo 应用领域
德州仪器 - TI 微控制器和处理器外围集成电路数字信号处理器时钟
页数 文件大小 规格书
269页 1414K
描述
TMS320C6472 Fixed-Point Digital Signal Processor

TMS320C6472ECTZA 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:BGA
包装说明:24 X 24 MM, 0.80 MM PITCH, GREEN, PLASTIC, FCBGA-737针数:737
Reach Compliance Code:compliantECCN代码:3A001.A.3
HTS代码:8542.31.00.01风险等级:5.26
Is Samacsys:N桶式移位器:NO
位大小:32边界扫描:YES
最大时钟频率:50 MHz格式:FIXED POINT
内部总线架构:MULTIPLEJESD-30 代码:S-PBGA-B737
JESD-609代码:e1长度:24 mm
低功率模式:YES湿度敏感等级:4
端子数量:737最高工作温度:100 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:FBGA封装等效代码:BGA737,29X29,32
封装形状:SQUARE封装形式:GRID ARRAY, FINE PITCH
峰值回流温度(摄氏度):245电源:1,1.2,1.8,3.3 V
认证状态:Not QualifiedRAM(字数):8192
座面最大高度:3.242 mm子类别:Digital Signal Processors
最大供电电压:1.05 V最小供电电压:0.95 V
标称供电电压:1 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Tin/Silver/Copper (Sn/Ag/Cu)端子形式:BALL
端子节距:0.8 mm端子位置:BOTTOM
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:24 mm
uPs/uCs/外围集成电路类型:DIGITAL SIGNAL PROCESSOR, OTHERBase Number Matches:1

TMS320C6472ECTZA 数据手册

 浏览型号TMS320C6472ECTZA的Datasheet PDF文件第2页浏览型号TMS320C6472ECTZA的Datasheet PDF文件第3页浏览型号TMS320C6472ECTZA的Datasheet PDF文件第4页浏览型号TMS320C6472ECTZA的Datasheet PDF文件第5页浏览型号TMS320C6472ECTZA的Datasheet PDF文件第6页浏览型号TMS320C6472ECTZA的Datasheet PDF文件第7页 
TMS320C6472  
www.ti.com  
SPRS612GJUNE 2009REVISED JULY 2011  
TMS320C6472 Fixed-Point Digital Signal Processor  
1 Features  
1
Congestion Control  
IEEE 1149.6 Compliant I/Os  
UTOPIA  
Six On-Chip TMS320C64x+ Megamodules  
Endianess: Little Endian, Big Endian  
C64x+ Megamodule Main Features:  
UTOPIA Level 2 Slave ATM Controller  
8/16-Bit Transmit and Receive  
High-Performance, Fixed-Point  
TMS320C64x+ DSP  
Operations up to 50 MHz per Direction  
500/625/700 MHz  
User-Defined Cell Format up to 64 Bytes  
Eight 32-Bit Instructions/Cycle  
4000 MIPS/MMACS (16-Bits) at 500 MHz  
Dedicated SPLOOP Instruction  
Compact Instructions (16-Bit)  
Instruction Set Enhancements  
Exception Handling  
Two 10/100/1000 Mb/s Ethernet MACs  
(EMACs)  
Both EMACs are IEEE 802.3 Compliant  
EMAC0 Supports:  
MII, RMII, SS-SMII, GMII, and RGMII  
8 Independent Transmit (TX)  
Channels  
L1/L2 Memory Architecture:  
256K-Bit (32K-Byte) L1P Program  
RAM/Cache [Direct Mapped, Flexible  
Allocation]  
256K-Bit (32K-Byte) L1D RAM/Cache  
[2-Way Set-Associative, Flexible  
Allocation]  
4.75M-Bit (608K-Byte) L2 Unified Mapped  
RAM/Cache [4-Way Set-Associative,  
Flexible Allocation]  
8 Independent Receive (RX)  
Channels  
EMAC1 Supports:  
RMII, SS-SMII and RGMII  
8 Independent Transmit (TX)  
Channels  
8 Independent Receive (RX)  
Channels  
L1P Memory Controller  
L1D Memory Controller  
L2 Memory Controller  
Both EMACs (EMAC0 and EMAC1) Share  
MDIO Interface  
16-Bit Host-Port Interface (HPI)  
One Inter-Integrated Circuit (I2C) Bus  
Six Shared 64-Bit General-Purpose Timers  
System PLL and PLL Controller  
Time Stamp Counter  
One 64-Bit General-Purpose/Watchdog Timer  
Shared Peripherals and Interfaces  
Secondary PLL and PLL Controller, Dedicated  
EDMA Controller  
to EMAC  
(64 Independent Channels)  
Third PLL and PLL Controller Dedicated to  
DDR2 Memory Controller  
16 General-Purpose I/O (GPIO) Pins  
IEEE-1149.1 (JTAG)  
Boundary-Scan-Compatible  
737-Pin Ball Grid Array (BGA) Package  
(CTZ or ZTZ Suffix), 0.8-mm Ball Pitch  
0.09-μm/7-Level Cu Metal Process (CMOS)  
3.3-, 1.8-, 1.5-, 1.2-V I/O Supplies  
1.0-/1.1-, 1.2-V Core Supplies  
Commercial Temperature [0°C to 85°C]  
Extended Temperature [-40°C to 100°C]  
Shared Memory Architecture  
Shared L2 Memory Controller  
768K-Byte of RAM  
Boot ROM  
Three Telecom Serial Interface Ports (TSIPs)  
Each TSIP is 8 Links of 8 Mbps per  
Direction  
32-Bit DDR2 Memory Controller (DDR2-533  
SDRAM)  
256 M-Byte x 2 Addressable Memory  
Space  
Two 1x Serial RapidIO® Links,  
v1.2 Compliant  
1.25-, 2.5-, 3.125-Gbps Link Rates  
Message Passing, DirectIO Support,  
Error Management Extensions, and  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
PRODUCT PREVIEW information concerns products in the formative  
or design phase of development. Characteristic data and other  
specifications are design goals. Texas Instruments reserves the right  
to change or discontinue these products without notice.  
Copyright © 2009–2011, Texas Instruments Incorporated  
 

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