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TMS320C6204GLWA-150 PDF预览

TMS320C6204GLWA-150

更新时间: 2024-10-27 14:45:15
品牌 Logo 应用领域
德州仪器 - TI 时钟外围集成电路
页数 文件大小 规格书
95页 1699K
描述
32-BIT, 150MHz, OTHER DSP, PBGA340, PLASTIC, BGA-340

TMS320C6204GLWA-150 技术参数

生命周期:Obsolete零件包装代码:BGA
包装说明:PLASTIC, BGA-340针数:340
Reach Compliance Code:unknownECCN代码:3A001.A.3
HTS代码:8542.31.00.01风险等级:5.71
Is Samacsys:N地址总线宽度:22
桶式移位器:NO边界扫描:YES
最大时钟频率:150 MHz外部数据总线宽度:32
格式:FIXED POINT内部总线架构:MULTIPLE
JESD-30 代码:S-PBGA-B340长度:18 mm
低功率模式:YES端子数量:340
最高工作温度:105 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:HFBGA
封装形状:SQUARE封装形式:GRID ARRAY, HEAT SINK/SLUG, FINE PITCH
认证状态:Not Qualified座面最大高度:2.095 mm
最大供电电压:1.575 V最小供电电压:1.425 V
标称供电电压:1.5 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子形式:BALL端子节距:0.8 mm
端子位置:BOTTOM宽度:18 mm
uPs/uCs/外围集成电路类型:DIGITAL SIGNAL PROCESSOR, OTHERBase Number Matches:1

TMS320C6204GLWA-150 数据手册

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TMS320C6204  
FIXED-POINT DIGITAL SIGNAL PROCESSOR  
SPRS152C -- OCTOBER 2000 -- REVISED MARCH 2004  
D
High-Performance Fixed-Point Digital  
Signal Processor (DSP) -- TMS320C6204  
-- 5-ns Instruction Cycle Time  
-- 200-MHz Clock Rate  
-- Eight 32-Bit Instructions/Cycle  
-- 1600 MIPS  
D
D
Four-Channel Bootloading  
Direct-Memory-Access (DMA) Controller  
With an Auxiliary Channel  
32-Bit Expansion Bus (XB)  
-- Glueless/Low-Glue Interface to Popular  
PCI Bridge Chips  
D
D
C6204 GLW Ball Grid Array (BGA) Package  
is Pin-Compatible With the C6202/02B/03  
GLS BGA Package†  
-- Glueless/Low-Glue Interface to Popular  
Synchronous or Asynchronous  
Microprocessor Buses  
-- Master/Slave Functionality  
-- Glueless Interface to Synchronous FIFOs  
and Asynchronous Peripherals  
VelociTIAdvanced Very-Long-Instruction-  
Word (VLIW) TMS320C62xDSP Core  
-- Eight Highly Independent Functional  
Units:  
D
Two Multichannel Buffered Serial Ports  
(McBSPs)  
-- Six ALUs (32-/40-Bit)  
-- Two 16-Bit Multipliers (32-Bit Result)  
-- Load-Store Architecture With 32 32-Bit  
General-Purpose Registers  
-- Instruction Packing Reduces Code Size  
-- All Instructions Conditional  
-- Direct Interface to T1/E1, MVIP, SCSA  
Framers  
-- ST-Bus-Switching Compatible  
-- Up to 256 Channels Each  
-- AC97-Compatible  
-- Serial-Peripheral Interface (SPI)  
Compatible (Motorola)  
D
D
D
Instruction Set Features  
-- Byte-Addressable (8-, 16-, 32-Bit Data)  
-- 8-Bit Overflow Protection  
-- Saturation  
-- Bit-Field Extract, Set, Clear  
-- Bit-Counting  
D
D
Two 32-Bit General-Purpose Timers  
Flexible Phase-Locked-Loop (PLL) Clock  
Generator  
IEEE-1149.1 (JTAG)  
D
-- Normalization  
Boundary-Scan-Compatible  
1M-Bit On-Chip SRAM  
-- 512K-Bit Internal Program/Cache  
(16K 32-Bit Instructions)  
-- 512K-Bit Dual-Access Internal Data  
(64K Bytes)  
D
D
D
288-Pin MicroStar BGAPackage (GHK)  
340-Pin BGA Package (GLW)  
0.15-μm/5-Level Metal Process  
-- CMOS Technology  
-- Organized as Two 32K-Byte Blocks for  
Improved Concurrency  
D
3.3-V I/Os, 1.5-V Internal  
32-Bit External Memory Interface (EMIF)  
-- Glueless Interface to Synchronous  
Memories: SDRAM or SBSRAM  
-- Glueless Interface to Asynchronous  
Memories: SRAM and EPROM  
-- 52M-Byte Addressable External Memory  
Space  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
VelociTI, TMS320C62x, and MicroStar BGA are trademarks of Texas Instruments.  
Motorola is a trademark of Motorola, Inc.  
For more details, see the GLW BGA package bottom view.  
IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
Copyright © 2004, Texas Instruments Incorporated  
1
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251--1443  

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