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TMS320C5515 PDF预览

TMS320C5515

更新时间: 2024-11-07 07:04:39
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德州仪器 - TI 数字信号处理器
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描述
TMS320C5515 Fixed-Point Digital Signal Processor

TMS320C5515 数据手册

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TMS320C5515  
www.ti.com  
SPRS645JANUARY 2010  
TMS320C5515 Fixed-Point Digital Signal Processor  
Check for Samples: TMS320C5515  
1 Fixed-Point Digital Signal Processor  
1.1 TMS320C5515 Features  
1
(4 Blocks of 16K x 16-Bit)  
• HIGHLIGHTS:  
• 4M x 16-Bit Maximum Addressable External  
Memory Space (SDRAM/mSDRAM)  
• 16-/8-Bit External Memory Interface (EMIF) with  
Glueless Interface to:  
– 8-/16-Bit NAND Flash, 1- and 4-Bit ECC  
– 8-/16-Bit NOR Flash  
– Asynchronous Static RAM (SRAM)  
– SDRAM/mSDRAM (1.8-, 2,5-, and 3.3-V)  
• Direct Memory Access (DMA) Controller  
– Four DMA With 4 Channels Each  
(16-Channels Total)  
• Three 32-Bit General-Purpose Timers  
– One Selectable as a Watchdog and/or GP  
• Two MultiMedia Card/Secure Digital (MMC/SD)  
Interfaces  
• High-Perf/Low-Power, C55x™ Fixed-Point DSP  
– 16.67/13.33/10/8.33-ns Instruction Cycle Time  
– 60-, 75-, 100-, 120-MHz Clock Rate  
• 320K Bytes On-Chip RAM  
• 16-/8-Bit External Memory Interface (EMIF)  
• Two MultiMedia Card/Secure Digital I/Fs  
• Serial-Port I/F (SPI) With Four Chip-Selects  
• Four Inter-IC Sound (I2S Bus™)  
• USB 2.0 Full- and High-Speed Device  
• LCD Bridge With Asynchronous Interface  
• Tightly-Coupled FFT Hardware Accelerator  
• 10-Bit 4-Input SAR ADC  
• Real-Time Clock (RTC) With Crystal Input  
• Four Core Isolated Power Supply Domains  
• Four I/O Isolated Power Supply Domains  
• Three integrated LDOs  
• Universal Asynchronous Receiver/Transmitter  
(UART)  
• Industrial Temperature Devices Available  
• 1.05-V Core, 1.8/2.5/2.8/3.3-V I/Os  
• 1.3-V Core, 1.8/2.5/2.8/3.3-V I/Os  
• FEATURES:  
• High-Performance, Low-Power, TMS320C55x™  
Fixed-Point Digital Signal Processor  
• Serial-Port Interface (SPI) With Four  
Chip-Selects  
• Master/Slave Inter-Integrated Circuit (I2C Bus™)  
• Four Inter-IC Sound (I2S Bus™) for Data  
Transport  
• Device USB Port With Integrated 2.0  
High-Speed PHY that Supports:  
– USB 2.0 Full- and High-Speed Device  
• LCD Bridge With Asynchronous Interface  
• Tightly-Coupled FFT Hardware Accelerator  
– 16.67-, 13.33, 10-, 8.33-ns Instruction Cycle  
Time  
– 60-, 75-, 100-, 120-MHz Clock Rate  
– One/Two Instruction(s) Executed per Cycle  
– Dual Multipliers [Up to 200 or 240 Million  
Multiply-Accumulates per Second (MMACS)]  
• 10-Bit 4-Input Successive Approximation (SAR)  
ADC  
– Two Arithmetic/Logic Units (ALUs)  
– Three Internal Data/Operand Read Buses  
and Two Internal Data/Operand Write Buses  
• Real-Time Clock (RTC) With Crystal Input, With  
Separate Clock Domain, Separate Power  
Supply  
• Four Core Isolated Power Supply Domains:  
Analog, RTC, CPU and Peripherals, and USB  
– Fully Software-Compatible With C55x  
Devices  
• Four I/O Isolated Power Supply Domains: RTC  
I/O, EMIF I/O, USB PHY, and DVDDIO  
• Three integrated LDOs (DSP_LDO, ANA_LDO,  
and USB_LDO) to power the isolated domains:  
DSP Core, Analog, and USB Core, respectively  
• Low-Power S/W Programmable Phase-Locked  
Loop (PLL) Clock Generator  
• On-Chip ROM Bootloader (RBL) to Boot From  
– Industrial Temperature Devices Available  
• 320 K Bytes Zero-Wait State On-Chip RAM,  
Composed of:  
– 64K Bytes of Dual-Access RAM (DARAM),  
8 Blocks of 4K x 16-Bit  
– 256K Bytes of Single-Access RAM (SARAM),  
32 Blocks of 4K x 16-Bit  
• 128K Bytes of Zero Wait-State On-Chip ROM  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
PRODUCT PREVIEW information concerns products in the formative  
Copyright © 2010, Texas Instruments Incorporated  
or design phase of development. Characteristic data and other  
specifications are design goals. Texas Instruments reserves the right  
to change or discontinue these products without notice.  
 
 

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