TMS320C5535
TMS320C5534, TMS320C5533, TMS320C5532
www.ti.com
SPRS737–AUGUST 2011
TMS320C5535, 'C5534, 'C5533, 'C5532 Fixed-Point Digital Signal Processors
Check for Samples: TMS320C5535, TMS320C5534, TMS320C5533, TMS320C5532
1 Fixed-Point Digital Signal Processor
1.1 Features
1
– Four Inter-IC Sound (I2S Bus™) for Data
Transport
– Device USB Port With Integrated 2.0
• CORE:
– High-Performance, Low-Power, TMS320C55x
Fixed-Point Digital Signal Processor
High-Speed PHY that Supports:
•
•
•
20-, 10-ns Instruction Cycle Time
50-, 100-MHz Clock Rate
One/Two Instruction(s) Executed per
Cycle
•
USB 2.0 Full- and High-Speed Device
– LCD Bridge With Asynchronous Interface
– 10-Bit 4-Input Successive Approximation
(SAR) ADC
– IEEE-1149.1 (JTAG™)
•
Dual Multipliers [Up to 200 Million
Multiply-Accumulates per Second
(MMACS)]
Boundary-Scan-Compatible
– Up to 20 General-Purpose I/O (GPIO) Pins
(Multiplexed With Other Device Functions)
• POWER:
•
•
Two Arithmetic/Logic Units (ALUs)
Three Internal Data/Operand Read Buses
and Two Internal Data/Operand Write
Buses
– Four Core Isolated Power Supply Domains:
Analog, RTC, CPU and Peripherals, and USB
– Three I/O Isolated Power Supply Domains:
•
•
Software-Compatible With C55x Devices
Industrial Temperature Devices Available
RTC I/O, USB PHY, and DVDDIO
– 320K Bytes Zero-Wait State On-Chip RAM,
– Three integrated LDOs (DSP_LDO,
ANA_LDO, and USB_LDO) to power the
isolated domains: DSP Core, Analog, and
USB Core, respectively
Composed of:
•
•
64K Bytes of Dual-Access RAM (DARAM),
8 Blocks of 4K x 16-Bit
256K Bytes of Single-Access RAM
(SARAM), 32 Blocks of 4K x 16-Bit
– 1.05-V Core (50 MHz), 1.8-V, 2.5-V, 2.75-V, or
3.3-V I/Os
– 128K Bytes of Zero Wait-State On-Chip ROM
– 1.3-V Core (100 MHz), 1.8-V, 2.5-V, 2.75-V, or
3.3-V I/Os
• CLOCK:
(4 Blocks of 16K x 16-Bit)
– Tightly-Coupled FFT Hardware Accelerator
• PERIPHERAL:
– Real-Time Clock (RTC) With Crystal Input,
With Separate Clock Domain, Separate
Power Supply
– Direct Memory Access (DMA) Controller
•
Four DMA With 4 Channels Each
(16-Channels Total)
– Low-Power S/W Programmable
– Three 32-Bit General-Purpose Timers
One Selectable as a Watchdog and/or GP
Phase-Locked Loop (PLL) Clock Generator
• BOOTLOADER:
•
– Two Embedded Multimedia Card/Secure
Digital (eMMC/SD) Interfaces
– Universal Asynchronous
Receiver/Transmitter (UART)
– Serial-Port Interface (SPI) With Four
Chip-Selects
– Master/Slave Inter-Integrated Circuit (I2C
Bus™)
– On-Chip ROM Bootloader (RBL) to Boot
From SPI EEPROM, SPI Serial Flash or I2C
EEPROM eMMC/SD/SDHC, UART, and USB
• PACKAGE:
– 144-Terminal Pb-Free Plastic BGA (Ball Grid
Array) (ZHH Suffix)
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Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2011, Texas Instruments Incorporated