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TMS320C44PDB40 PDF预览

TMS320C44PDB40

更新时间： 2024-11-24 15:54:47
品牌 Logo 应用领域
德州仪器 - TI 时钟外围集成电路装置
页数 文件大小 规格书
42页 623K
描述
32-BIT, 40MHz, OTHER DSP, PQFP304

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中文翻译

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TMS320C44PDB40 技术参数

生命周期：Obsolete包装说明：QFP,
Reach Compliance Code：unknownECCN代码：3A991.A.2
HTS代码：8542.31.00.01风险等级：5.83
地址总线宽度：24桶式移位器：YES
边界扫描：YES最大时钟频率：40 MHz
外部数据总线宽度：32格式：FLOATING POINT
集成缓存：NO内部总线架构：MULTIPLE
JESD-30 代码：S-PQFP-G304低功率模式：YES
DMA 通道数量：6外部中断装置数量：5
串行 I/O 数：端子数量：304
计时器数量：2片上数据RAM宽度：8
片上程序ROM宽度：最高工作温度：85 °C
最低工作温度：封装主体材料：PLASTIC/EPOXY
封装代码：QFP封装形状：SQUARE
封装形式：FLATPACK认证状态：Not Qualified
RAM（字数）：4096最大压摆率：850 mA
最大供电电压：5.25 V最小供电电压：4.75 V
标称供电电压：5 V表面贴装：YES
技术：CMOS温度等级：OTHER
端子形式：GULL WING端子位置：QUAD
uPs/uCs/外围集成电路类型：DIGITAL SIGNAL PROCESSOR, OTHERBase Number Matches：1

TMS320C44PDB40 数据手册

 浏览型号TMS320C44PDB40的Datasheet PDF文件第2页浏览型号TMS320C44PDB40的Datasheet PDF文件第3页浏览型号TMS320C44PDB40的Datasheet PDF文件第4页浏览型号TMS320C44PDB40的Datasheet PDF文件第5页浏览型号TMS320C44PDB40的Datasheet PDF文件第6页浏览型号TMS320C44PDB40的Datasheet PDF文件第7页 
TMS320C44  
DIGITAL SIGNAL PROCESSOR  
SPRS031B – AUGUST 1994 – REVISED DECEMBER 1995  
PDB PACKAGE  
(TOP VIEW)  
Highest Performance Floating-Point Digital  
Signal Processor (DSP)  
‡
– TMS320C44-60:  
304  
229  
33-ns Instruction Cycle Time,  
330 MOPS, 60 MFLOPS,  
30 MIPS, 336M Bytes/s  
1
228  
– TMS320C44-50:  
40-ns Instruction Cycle Time  
Four Communication Ports  
Six-Channel Direct Memory Address (DMA)  
Coprocessor  
Single-Cycle Conversion to and From  
IEEE-754 Floating-Point Format  
Single Cycle, 1/x, 1/√x  
Source-Code Compatible With ’320C3x and  
’320C4x  
Single-Cycle 40-Bit Floating-Point,  
32-Bit Integer Multipliers  
Twelve 40-Bit Registers, Eight Auxiliary  
Registers, 14 Control Registers,  
and Two Timers  
†
IEEE-1149.1 (JTAG) Boundary-Scan  
Compatible  
76  
153  
77  
152  
Two Identical External Data and Address  
Buses Supporting Shared Memory  
Systems and High Data-Rate,  
Single-Cycle Transfers  
‡
SeePin Assignments table and Pin Functions table for location  
and description of all pins.  
– High Port-Data Rate of 120M Bytes/s  
(TMS320C44-60) (Each Bus)  
– 128M-Byte Program/Data/Peripheral  
Address Space  
– Memory-Access Request for Fast,  
Intelligent Bus Arbitration  
– Separate Address-Bus, Data-Bus, and  
Control-Enable Pins  
– Four Sets of Memory-Control Signals  
Support Different Speed Memories in  
Hardware  
IDLE2 Clock-Stop Power-Down Mode  
Communication-Port-Direction Pin  
On-Chip Program Cache and  
Dual-Access/Single-Cycle RAM for  
Increased Memory-Access Performance  
– 512-Byte Instruction Cache  
– 8K Bytes of Single-Cycle Dual-Access  
Program or Data RAM  
– ROM-Based Boot Loader Supports  
Program Bootup Using 8-, 16-, or 32-Bit  
Memories or One of the Communication  
Ports  
304-Pin Plastic Quad Flatpack  
(PDB Suffix)  
Fabricated Using 0.72-µm Enhanced  
Performance Implanted CMOS (EPIC )  
Technology by Texas Instruments (TI )  
Separate Internal Program-, Data-, and  
DMA-Coprocessor Buses for Support of  
Massive Concurrent I/O of Program and  
Data, Thereby Maximizing Sustained CPU  
Performance  
Software-Communication-Port Reset  
NMI With Bus-Grant Feature  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
†
IEEE Standard 1149.1–1990 Standard Test-Access Port and Boundary-Scan Architecture  
EPIC and TI are trademarks of Texas Instruments Incorporated.  
Copyright 1995, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443  
1234567...42

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