Datasheet > TMS320C44PDB-60

TMS320C44PDB-60

更新时间： 2024-11-23 23:36:27

品牌	Logo	应用领域
其他 - ETC		/
页数	文件大小	规格书
42页	627K
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DSP\|32-BIT\|CMOS\|QFP\|304PIN\|PLASTIC

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TMS320C44PDB-60 数据手册

TMS320C44

DIGITAL SIGNAL PROCESSOR

SPRS031B – AUGUST 1994 – REVISED DECEMBER 1995

PDB PACKAGE

(TOP VIEW)

Highest Performance Floating-Point Digital

Signal Processor (DSP)

‡

– TMS320C44-60:

304

229

33-ns Instruction Cycle Time,

330 MOPS, 60 MFLOPS,

30 MIPS, 336M Bytes/s

228

– TMS320C44-50:

40-ns Instruction Cycle Time

Four Communication Ports

Six-Channel Direct Memory Address (DMA)

Coprocessor

Single-Cycle Conversion to and From

IEEE-754 Floating-Point Format

Single Cycle, 1/x, 1/√x

Source-Code Compatible With ’320C3x and

’320C4x

Single-Cycle 40-Bit Floating-Point,

32-Bit Integer Multipliers

Twelve 40-Bit Registers, Eight Auxiliary

Registers, 14 Control Registers,

and Two Timers

†

IEEE-1149.1 (JTAG) Boundary-Scan

Compatible

153

152

Two Identical External Data and Address

Buses Supporting Shared Memory

Systems and High Data-Rate,

Single-Cycle Transfers

‡

SeePin Assignments table and Pin Functions table for location

and description of all pins.

– High Port-Data Rate of 120M Bytes/s

(TMS320C44-60) (Each Bus)

– 128M-Byte Program/Data/Peripheral

Address Space

– Memory-Access Request for Fast,

Intelligent Bus Arbitration

– Separate Address-Bus, Data-Bus, and

Control-Enable Pins

– Four Sets of Memory-Control Signals

Support Different Speed Memories in

Hardware

IDLE2 Clock-Stop Power-Down Mode

Communication-Port-Direction Pin

On-Chip Program Cache and

Dual-Access/Single-Cycle RAM for

Increased Memory-Access Performance

– 512-Byte Instruction Cache

– 8K Bytes of Single-Cycle Dual-Access

Program or Data RAM

– ROM-Based Boot Loader Supports

Program Bootup Using 8-, 16-, or 32-Bit

Memories or One of the Communication

Ports

304-Pin Plastic Quad Flatpack

(PDB Suffix)

Fabricated Using 0.72-µm Enhanced

Performance Implanted CMOS (EPIC )

Technology by Texas Instruments (TI )

Separate Internal Program-, Data-, and

DMA-Coprocessor Buses for Support of

Massive Concurrent I/O of Program and

Data, Thereby Maximizing Sustained CPU

Performance

Software-Communication-Port Reset

NMI With Bus-Grant Feature

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

†

IEEE Standard 1149.1–1990 Standard Test-Access Port and Boundary-Scan Architecture

EPIC and TI are trademarks of Texas Instruments Incorporated.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

12 3 4 5 6 7...42

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与TMS320C44PDB-60相关器件

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