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TMS320C40TABL60 PDF预览

TMS320C40TABL60

更新时间： 2024-11-24 20:59:27
品牌 Logo 应用领域
德州仪器 - TI 时钟外围集成电路装置
页数 文件大小 规格书
44页 702K
描述
32-BIT, 60MHz, OTHER DSP, UUC325

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TMS320C40TABL60 技术参数

生命周期：ObsoleteReach Compliance Code：unknown
ECCN代码：3A001.A.3HTS代码：8542.31.00.01
风险等级：5.77Is Samacsys：N
地址总线宽度：31桶式移位器：YES
位大小：32边界扫描：YES
最大时钟频率：60 MHz外部数据总线宽度：32
格式：FLOATING POINT集成缓存：NO
内部总线架构：MULTIPLEJESD-30 代码：S-XUUC-N325
低功率模式：NODMA 通道数量：6
外部中断装置数量：5串行 I/O 数：
端子数量：325计时器数量：2
片上数据RAM宽度：32片上程序ROM宽度：
最高工作温度：70 °C最低工作温度：
封装主体材料：UNSPECIFIED封装代码：DIE
封装等效代码：TAB,325PINS,.01封装形状：SQUARE
封装形式：UNCASED CHIP电源：5 V
认证状态：Not QualifiedRAM（字数）：1024
子类别：Digital Signal Processors最大压摆率：850 mA
最大供电电压：5.25 V最小供电电压：4.75 V
标称供电电压：5 V表面贴装：YES
技术：CMOS温度等级：COMMERCIAL
端子形式：NO LEAD端子节距：0.254 mm
端子位置：UPPERuPs/uCs/外围集成电路类型：DIGITAL SIGNAL PROCESSOR, OTHER
Base Number Matches：1

TMS320C40TABL60 数据手册

 浏览型号TMS320C40TABL60的Datasheet PDF文件第2页浏览型号TMS320C40TABL60的Datasheet PDF文件第3页浏览型号TMS320C40TABL60的Datasheet PDF文件第4页浏览型号TMS320C40TABL60的Datasheet PDF文件第5页浏览型号TMS320C40TABL60的Datasheet PDF文件第6页浏览型号TMS320C40TABL60的Datasheet PDF文件第7页 
TMS320C40  
DIGITAL SIGNAL PROCESSOR  
SPRS038 – JANUARY 1996  
325-PIN GF GRID ARRAY PACKAGE  
Highest Performance Floating-Point Digital  
Signal Processor (DSP)  
– ’320C40-60:  
33-ns Instruction Cycle Time,  
330 MOPS, 60 MFLOPS,  
30 MIPS, 384M Bytes/s  
– ’320C40-50:  
‡
(BOTTOM VIEW)  
AR  
AP  
AN  
AM  
AL  
AK  
AJ  
AH  
AG  
AF  
AE  
AD  
AC  
AB  
AA  
40-ns Instruction Cycle Time  
– ’320C40-40:  
50-ns Instruction Cycle Time  
Y
W
U
R
N
Six Communications Ports  
V
T
P
Six-Channel Direct Memory Access (DMA)  
Coprocessor  
M
K
H
F
L
J
Single-Cycle Conversion to and From  
IEEE-754 Floating-Point Format  
G
E
C
A
Single Cycle, 1/x, 1/ x  
D
B
Source-Code Compatible With TMS320C3x  
Single-Cycle 40-Bit Floating-Point,  
32-Bit Integer Multipliers  
2
4
6
8
10 12 14 16 18 20 22 24 26 28 30 32 34  
9
11 13 15 17 19 21 23 25 27 29 31 33 35  
1
3
5
7
Pin A1  
Twelve 40-Bit Registers, Eight Auxiliary  
Registers, 14 Control Registers, and Two  
Timers  
‡
See Pin Assignments table and Pin Functions table for location  
and description of all pins.  
†
IEEE 1149.1 (JTAG) Boundary Scan  
Compatible  
Two Identical External Data and Address  
Buses Supporting Shared Memory Systems  
and High Data-Rate, Single-Cycle  
Transfers:  
– High Port-Data Rate of 120M Bytes/s  
(’C40-60) (Each Bus)  
Separate Internal Program, Data, and DMA  
Coprocessor Buses for Support of Massive  
Concurrent Input/Output (I/O) of Program  
and Data Throughput, Maximizing  
Sustained Central Processing Unit (CPU)  
Performance  
– 16G-Byte Continuous  
Program/Data/Peripheral Address  
Space  
– Memory-Access Request for Fast,  
Intelligent Bus Arbitration  
– Separate Address-Bus, Data-Bus, and  
Control-Enable Pins  
– Four Sets of Memory-Control Signals  
Support Different Speed Memories in  
Hardware  
On-Chip Program Cache and  
Dual-Access/Single-Cycle RAM for  
Increased Memory-Access Performance  
– 512-Byte Instruction Cache  
– 8K Bytes of Single-Cycle Dual-Access  
Program or Data RAM  
– ROM-Based Boot Loader Supports  
Program Bootup Using 8-, 16-, or 32-Bit  
Memories or One of the Communication  
Ports  
325-Pin Ceramic Grid Array (GF Suffix)  
Fabricated Using 0.72-µm Enhanced  
Performance Implanted CMOS (EPIC )  
Technology by Texas Instruments (TI )  
IDLE2 Clock-Stop Power-Down Mode  
5-V Operation  
Software-Communication-Port Reset  
NMI With Bus-Grant Feature  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
†
IEEE Standard 1149.1–1990 Standard Test-Access Port and Boundary-Scan Architecture  
EPIC and TI are trademarks of Texas Instruments Incorporated.  
Copyright 1996, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443  
1234567...44

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