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TMS29LF040

更新时间： 2024-11-07 22:50:27
品牌 Logo 应用领域
德州仪器 - TI 闪存
页数 文件大小 规格书
38页 493K
描述
524288 BY 8-BIT FLASH MEMORIES

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TMS29LF040 数据手册

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TMS29LF040, TMS29VF040  
524288 BY 8-BIT  
FLASH MEMORIES  
SMJS825D – SEPTEMBER 1995 – REVISED JUNE 1998  
FM PACKAGE  
(TOP VIEW)  
Single Power Supply  
3.3 V ± 0.3 V – TMS29LF040  
2.7 V to 3.6 V – TMS29VF040  
5 V ± 10% – See TMS29F040 Data sheet  
(Literature Number SMJS820)  
4
3 2 1 32 31 30  
Organization . . . 524288 By 8 Bits  
5
29  
28  
27  
26  
25  
24  
23  
22  
21  
A7  
A6  
A14  
A13  
A8  
6
Eight Equal Sectors of 64K Bytes  
– Any Combination of Sectors Can Be  
Erased  
– Any Combination of Sectors Can Be  
Marked as Read-Only  
7
A5  
8
A4  
A9  
9
A3  
A11  
G
10  
11  
12  
13  
A2  
A1  
A10  
E
Compatible With JEDEC Electrically  
Erasable Programmable Read-Only  
Memory (EEPROM) Command Set  
A0  
DQ0  
DQ7  
14 15 16 17 18 19 20  
Fully Automated On-Chip Erase and  
Byte-Program Operations  
100000 Program/Erase Cycles  
Erase-Suspend/Erase-Resume Operation  
Compatible With JEDEC Byte-Wide Pinouts  
PIN NOMENCLATURE  
A[0:18]  
DQ[0:7]  
E
Address Inputs  
Low-Current Consumption  
– Active Read . . . 20 mA Typical  
– Active Program/Erase . . . 30 mA Typical  
Inputs (programming)/Outputs  
Chip Enable  
G
Output Enable  
Power Supply  
Ground  
V
All Inputs/Outputs CMOS-Compatible Only  
CC  
V
SS  
W
Write Enable  
description  
The TMS29LF040 and TMS29VF040 are 524288 by 8-bit (4194304-bit), low-voltage, single-supply,  
programmable read-only memories that can be erased electrically and reprogrammed. These devices are  
organized as eight independent 64K-byte sectors and are offered with access times between 80 ns and  
150 ns.  
An on-chip state machine controls the program and erase operations. The embedded-byte program and  
sector/chip-erase functions are fully automatic. The command set is compatible with that of JEDEC 4M-bit  
EEPROMs. A suspend/resume feature allows access to unaltered memory sectors during a sector-erase  
operation. Data protection of any sector combination is accomplished using a hardware sector-protection  
feature.  
Device operations are selected by writing JEDEC-standard commands into the command register using  
standard microprocessor-write timings. The command register acts as input to an internal state machine that  
interprets the commands, controls the erase and programming operations, and outputs the status of the device,  
the data stored in the device, and the device algorithm-selection code. On initial power-up operation, the device  
defaults to the read mode.  
The TMS29xF040 is offered in a 32-pin 8 x 14 mm thin small-outline package (DBW suffix), a 32-pin  
8 x 20 mm thin small-outline package (DD suffix), and a 32-pin plastic leaded chip carrier (FM suffix) using  
1.27 mm (50-mil) lead pitch.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 1998, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443  
1234567...38

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TMS29LF040-10C5DDE4 TI

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TMS29LF040-10C5DDL TI

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TMS29LF040-10C5DDL4 TI

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TMS29LF040-10C5DUL TI

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 		512KX8 FLASH 3V PROM, 100ns, PDSO32

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