TM4100EAD9
4194304 BY 9-BIT
DYNAMIC RAM MODULE
SMMS419C – NOVEMBER 1991 – REVISED JUNE 1995
timing requirements over recommended ranges of supply voltage and operating free-air
temperature
’4100EAD9-60
’4100EAD9-70
’4100EAD9-80
UNIT
MIN
110
40
MAX
MIN
130
45
MAX
MIN
150
50
MAX
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Cycle time, random read or write (see Note 7)
Cycle time, page-mode read or write (see Note 8)
Pulse duration, page mode RAS low (see Note 9)
Pulse duration, nonpage mode, RAS low (see Note 9)
Pulse duration, CAS low (see Note 10)
Pulse duration, CAS high
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
RC
PC
60 100 000
70 100 000
80 100 000
RASP
RAS
CAS
CP
60
15
10
40
15
0
10 000
10 000
70
18
10
50
15
0
10 000
10 000
80
20
10
60
15
0
10 000
10 000
Pulse duration, RAS high (precharge)
Pulse duration, write
RP
WP
Setup time, column address before CAS low
Setup time, row address before RAS low
Setup time, data (see Note 11)
ASC
ASR
DS
0
0
0
0
0
0
Setup time, read before CAS low
0
0
0
RCS
CWL
RWL
WCS
WSR
WTS
CAH
DHR
DH
Setup time, W low before CAS high
15
15
0
18
18
0
20
20
0
Setup time, W low before RAS high
Setup time, W low before CAS low (early-write operation only)
Setup time, W high (CBR refresh only)
Setup time, W low (test mode only)
10
10
10
50
10
50
10
0
10
10
15
55
15
55
10
0
10
10
15
60
15
60
10
0
Hold time, column address after CAS low
Hold time, data after RAS low (see Note 12)
Hold time, data (see Note 10)
Hold time, column address after RAS low (see Note 12)
Hold time, row address after RAS low
Hold time, read after CAS high (see Note 13)
Hold time, read after RAS high (see Note 13)
Hold time, write after CAS low (early-write operation only)
Hold time, write after RAS low (see Note 12)
Hold time, W high (CBR refresh only)
AR
RAH
RCH
RRH
WCH
WCR
WHR
WTH
0
0
0
15
50
10
10
15
55
10
10
15
60
10
10
Hold time, W low (test mode only)
t
t
t
t
Delay time, RAS low to CAS high (CBR refresh only)
Delay time, CAS high to RAS low
15
0
15
0
20
0
ns
ns
ns
ns
CHR
CRP
CSH
CSR
Delay time, RAS low to CAS high
60
10
70
10
80
10
Delay time, CAS low to RAS low (CBR refresh only)
NOTES: 7. All cycle times assume t = 5 ns.
T
ASC
RWD
CWD
8. To assure t
9. In a read-write cycle, t
10. In a read-write cycle, t
min, t
should be ≥ 5 ns.
PC
and t
and t
must be observed.
must be observed.
RWL
CWL
11. Referenced to the later of CAS or W in write operations
12. The minimum value is measured when t
is set to t min as a reference.
RCD
RCD
must be satisfied for a read cycle.
13. Either t
RRH
or t
RCH
6
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443