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TM2SR72EPU

更新时间： 2024-02-21 15:14:44

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德州仪器 - TI		/
页数	文件大小	规格书
46页	887K
描述
SYNCHRONOUS DYNAMIC RAM MODULES

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技术参数
数据手册

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TM2SR72EPU 技术参数

生命周期：	Obsolete	零件包装代码：	DIMM
包装说明：	,	针数：	168
Reach Compliance Code：	unknown	ECCN代码：	EAR99
HTS代码：	8542.32.00.24	风险等级：	5.84
访问模式：	DUAL BANK PAGE BURST	最长访问时间：	7.5 ns
JESD-30 代码：	R-XDMA-N168	内存密度：	150994944 bit
内存集成电路类型：	SYNCHRONOUS DRAM MODULE	内存宽度：	72
功能数量：	1	端口数量：	1
端子数量：	168	字数：	2097152 words
字数代码：	2000000	工作模式：	SYNCHRONOUS
最高工作温度：	70 °C	最低工作温度：
组织：	2MX72	封装主体材料：	UNSPECIFIED
封装形状：	RECTANGULAR	封装形式：	MICROELECTRONIC ASSEMBLY
认证状态：	Not Qualified	最大供电电压 (Vsup)：	3.6 V
最小供电电压 (Vsup)：	3 V	标称供电电压 (Vsup)：	3.3 V
表面贴装：	NO	技术：	CMOS
温度等级：	COMMERCIAL	端子形式：	NO LEAD
端子位置：	DUAL	Base Number Matches：	1

TM2SR72EPU 数据手册

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SMMS683A − JUNE 1997 − REVISED AUGUST 1997

serial presence detect (continued)

Table 2. Serial Presence-Detect Data for the TM4SR72EPU

TM4SR72EPU-12A

TM4SR72EPU-12

BYTE

NO.

DESCRIPTION OF FUNCTION

ITEM

DATA

ITEM

DATA

Defines number of bytes written into serial memory during

module manufacturing

128 bytes

80h

128 bytes

80h

Total number of bytes of SPD memory device

Fundamental memory type (FPM, EDO, SDRAM, . . .)

Number of row addresses on this assembly

Number of column addresses on this assembly

Number of module banks on this assembly

Data width of this assembly

256 bytes

SDRAM

08h

04h

0Bh

09h

02h

48h

00h

01h

256 bytes

SDRAM

08h

04h

0Bh

09h

02h

48h

00h

01h

2 banks

72 bits

2 banks

72 bits

Data width continuation

Voltage interface standard of this assembly

LVTTL

SDRAM cycle time at maximum supported CAS latency

(CL), CL = X

= 12 ns

= 9 ns

C0h

90h

02h

= 12 ns

= 9 ns

C0h

90h

02h

SDRAM access from clock at CL = X

DIMM configuration type (non-parity, parity, error correcting

code [ECC])

ECC

15.6 µs/

self-refresh

15.6 µs/

self-refresh

Refresh rate/type

80h

SDRAM width, primary DRAM

08h

Error-checking SDRAM data width

Minimum clock delay, back-to-back random column

addresses

1 CK cycle

01h

1 CK cycle

01h

Burst lengths supported

Number of banks on each SDRAM device

CAS latencies supported

CS latency

1, 2, 4, 8

0Fh

02h

06h

01h

1, 2, 4, 8

0Fh

02h

06h

01h

2 banks

2, 3

Write latency

Non-buffered/

Non-registered

Non-buffered/

Non-registered

SDRAM module attributes

00h

tolerance =

(+10%),

(+10%)/(−5%).

Burst read/write,

precharge all,

Burst read/write,

precharge all,

SDRAM device attributes: general

1Eh

0Eh

auto precharge

Minimum clock cycle time at CL = X − 1

Maximum data-access time from clock at CL = X − 1

Minimum clock cycle time at CL = X − 2

Maximum data-access time from clock at CL = X − 2

Minimum row precharge time

= 15 ns

= 9.0 ns

N/A

F0h

90h

00h

1Eh

18h

1Eh

3Ch

04h

= 18 ns

= 10 ns

N/A

30h

A0h

00h

24h

18h

1Eh

48h

04h

N/A

= 30 ns

= 36 ns

Minimum row-active to row-active delay

Minimum RAS-to-CAS delay

= 24 ns

= 30 ns

= 60 ns

= 24 ns

= 30 ns

= 72 ns

RRD

RCD

Minimum RAS pulse width

RAS

Density of each bank on module

16M Bytes

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