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TLV320VD30PN PDF预览

TLV320VD30PN

更新时间： 2024-11-24 22:08:31
品牌 Logo 应用领域
德州仪器 - TI 解码器编解码器电信集成电路电信电路
页数 文件大小 规格书
21页 263K
描述
VDSL CODEC

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中文翻译

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TLV320VD30PN 技术参数

是否无铅： 含铅生命周期：Obsolete
零件包装代码：QFP包装说明：PLASTIC, QFP-80
针数：80Reach Compliance Code：compliant
HTS代码：8542.39.00.01风险等级：5.68
Is Samacsys：N数据速率：52000 Mbps
JESD-30 代码：S-PQFP-G80长度：12 mm
功能数量：1端子数量：80
最高工作温度：85 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装代码：LFQFP
封装等效代码：QFP80,.55SQ,20封装形状：SQUARE
封装形式：FLATPACK, LOW PROFILE, FINE PITCH电源：2.5/3.3,3.3 V
认证状态：Not Qualified座面最大高度：1.6 mm
子类别：Other Telecom ICs标称供电电压：3.3 V
表面贴装：YES电信集成电路类型：TELECOM CIRCUIT
温度等级：INDUSTRIAL端子形式：GULL WING
端子节距：0.5 mm端子位置：QUAD
宽度：12 mmBase Number Matches：1

TLV320VD30PN 数据手册

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TLV320VD30  
VDSL CODEC  
SLWS086 – JUNE 1999  
General-Purpose Analog Interface Circuit  
for VDSL System  
26 dB RFI Suppression  
Programmable Receive Amplifier Operating  
From 0 dB to 20 dB, in Steps of 1 dB  
12 Bit, 22 MHz ADC and DAC  
Provides 11 MHz Bandwidth Performance  
Programmable Transmitter Output Power  
Level From –13 dBm to 11 dBm  
Supports Central Office and Remote  
Terminal Applications  
Enable/Disable of All Major Blocks During  
Power Mode  
Excellent Power Management by  
Enabling/Disabling Major Functional  
Blocks When in Power Control Mode  
Digital Loopback Test Mode  
Internal Voltage References  
Serial Control Port  
Remote Activation Feature With Selectable  
Wake-Up Tone Frequency  
Conversion Rate up to 22.08 MHz  
Integrated Equalizer to Partially  
Compensate for the Roll Off in Twisted Pair  
Telephone Cable  
Selectable Offset Binary or 2s Complement  
Data Format  
3.3 V Operation  
Numerically Controlled Oscillator With  
Resolution <1 ppm, Range of 250 ppm  
Using External Crystal  
80-Pin PN Package  
description  
The TLV320VD30 is an analog front end (AFE) device for VDSL systems. The TLV320VD30 provides a  
transmitter and a receiver. Both the transmitter and receiver have up to 11 MHz-bandwidth performance. The  
device can be used for central office and remote VDSL applications. The transmitter consists of a 12-bit/22 MHz  
DAC and a programmable line driver interface. The receiver consists of a 12-bit/22 MHz ADC, a programmable  
gainamplifier, acompromiseequalizer, andanRFIcancellationcircuit. Thedeviceincludesatonedetectcircuit,  
and a numerically controlled crystal oscillator.  
The TLV320VD30 provides two parallel ports for fast data transfers and a serial port for device control. The  
parallel ports are 12-pin ports with data transfer rates of up to 22 MHz per 12-bit word. One parallel port is  
dedicated to DAC input, the other parallel port is dedicated to ADC output. The serial port supports both write  
and read operations. The serial data transfer rate is 1.38 MHz per bit. Data is transferred in 16-bit words.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 1999, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...21

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