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TLV320AIC3254_14

更新时间: 2024-11-09 02:58:23
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德州仪器 - TI /
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描述
Ultra Low Power Stereo Audio Codec

TLV320AIC3254_14 数据手册

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TLV320AIC3254  
Ultra Low Power Stereo Audio Codec With Embedded miniDSP  
www.ti.com  
SLAS549ASEPTEMBER 2008REVISED OCTOBER 2008  
1 Introduction  
1.1 Features  
1.2 Applications  
Stereo Audio DAC with 100dB SNR  
4.1mW Stereo 48ksps DAC Playback  
Stereo Audio ADC with 93dB SNR  
6.1mW Stereo 48ksps ADC Record  
PowerTune™  
Portable Navigation Devices (PND)  
Portable Media Player (PMP)  
Mobile Handsets  
Communication  
Portable Computing  
Extensive Signal Processing Options  
Embedded miniDSP  
Acoustic Echo Cancellation (AEC)  
Active Noise Cancellation (ANC)  
Advanced DSP algorithms  
Six Single-Ended or 3 Fully-Differential Analog  
Inputs  
Stereo Analog and Digital Microphone Inputs  
Stereo Headphone Outputs  
Stereo Line Outputs  
1.3 Description  
The TLV320AIC3254 (sometimes referred to as the  
AIC3254) is a flexible, low-power, low-voltage stereo  
audio codec with programmable inputs and outputs,  
PowerTune capabilities, fully programmable miniDSP,  
fixed predefined and parameterizable signal  
processing blocks, integrated PLL, integrated LDOs  
and flexible digital interfaces.  
Very Low-Noise PGA  
Low Power Analog Bypass Mode  
Programmable Microphone Bias  
Programmable PLL  
Integrated LDO  
5 mm x 5 mm 32-pin QFN Package  
IN1_L  
-72...0dB  
Vol. Ctrl  
IN2_L  
AGC  
DRC  
-6...+29dB  
0…+47.5 dB  
IN3_L  
+
+
ADC  
Signal  
Proc.  
DAC  
Signal  
Proc.  
+
+
+
+
HPL  
LOL  
LOR  
HPR  
Left  
ADC  
Left  
DAC  
tpl  
´
´
1dB steps  
-6...+29dB  
Gain Adj.  
0.5 dB  
steps  
-30...0 dB  
1dB steps  
-6...+29dB  
Data  
Interface  
miniDSP  
miniDSP  
-30...0 dB  
1dB steps  
-6...+29dB  
0…  
+47.5 dB  
Gain Adj.  
+
+
ADC  
Signal  
Proc.  
DAC  
Signal  
Proc.  
Right  
ADC  
Right  
DAC  
tpr  
´
´
IN3_R  
IN2_R  
IN1_R  
0.5 dB steps  
AGC  
DRC  
Vol. Ctrl  
1dB steps  
-72...0dB  
SPI_Select  
Reset  
SPI / I2C  
Control Block  
Digital Interrupt Secondary  
Mic. Ctrl  
I2S IF  
Primary  
I2S Interface  
PLL  
HPVdd  
MicBias  
Ref  
Mic  
Bias  
ALDO  
Supplies  
Pin Muxing/ Clock Routing  
Ref  
DLDO  
Figure 1-1. Simplified Block Diagram  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this document.  
PowerTune is a trademark of Texas Instruments.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
Copyright © 2008–2008, Texas Instruments Incorporated  
 

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