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TLV320AIC3256_14

更新时间： 2024-11-11 02:58:15
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德州仪器 - TI /
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描述
Ultra Low Power Stereo Audio Codec With Embedded miniDSP

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TLV320AIC3256  
www.ti.com  
SLOS630A –DECEMBER 2010–REVISED DECEMBER 2010  
Ultra Low Power Stereo Audio Codec With Embedded miniDSP  
Check for Samples: TLV320AIC3256  
1
FEATURES  
•
Future 3.5mm x 3.3mm 42-ball WCSP  
2
•
Stereo Audio DAC with 100dB SNR  
APPLICATIONS  
•
5.0mW Stereo 48ksps  
•
•
•
•
•
•
•
•
Portable Navigation Devices (PND)  
Portable Media Player (PMP)  
Mobile Handsets  
Communication  
Portable Computing  
Acoustic Echo Cancellation (AEC)  
Active Noise Cancellation (ANC)  
Advanced DSP algorithms  
DAC-to-Ground-Centered Headphone Playback  
•
•
•
•
•
•
Stereo Audio ADC with 93dB SNR  
5.2mW Stereo 48ksps ADC Record  
PowerTune™  
Extensive Signal Processing Options  
Embedded miniDSP  
Six Single-Ended or 3 Fully-Differential Analog  
Inputs  
•
•
•
•
•
•
•
Stereo Analog and Digital Microphone Inputs  
Ground-Centered Stereo Headphone Outputs  
Very Low-Noise PGA  
DESCRIPTION  
The TLV320AIC3256 (sometimes referred to as the  
AIC3256) is a flexible, low-power, low-voltage stereo  
audio codec with programmable inputs and outputs,  
PowerTune capabilities, fully-programmable miniDSP,  
fixed predefined and parameterizable signal  
processing blocks, integrated PLL, and flexible digital  
interfaces.  
Low Power Analog Bypass Mode  
Programmable Microphone Bias  
Programmable PLL  
5mm x 5mm 40-pin QFN Package  
IN1_L  
IN2_L  
IN3_L  
AGC  
DRC  
Vol. Ctrl  
-6...+14dB  
0…+47.5 dB  
+
+
ADC  
Signal  
Proc.  
DAC  
Signal  
Proc.  
HPL  
LOL  
LOR  
+
+
+
+
Left  
ADC  
Left  
DAC  
tpl  
*
*
1dB steps  
-6...+29dB  
Gain Adj.  
0.5 dB  
steps  
-30...0 dB  
1dB steps  
-6...+29dB  
Data  
Interface  
miniDSP  
miniDSP  
-30...0 dB  
1dB steps  
-6...+14dB  
0…  
+47.5 dB  
Gain Adj.  
+
+
ADC  
Signal  
Proc.  
DAC  
Signal  
Proc.  
Right  
ADC  
Right  
DAC  
tpr  
*
*
HPR  
IN3_R  
IN2_R  
IN1_R  
0.5 dB steps  
AGC  
DRC  
1dB steps  
Vol. Ctrl  
GND_Sense  
SPI_Select  
Reset  
SPI / I2C  
Control Block  
Dig Inter  
Mic rupt  
Sec.  
I2S I/F  
Primary  
I2S Interface  
PLL  
VNEG  
Fly_N  
Fly_P  
Charge  
Pump  
MicBias  
MicDet  
Mic  
Bias  
Supplies  
Pin Muxing/ Clock Routing  
Ref  
Ref  
Figure 1. Simplified Block Diagram  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
2
PowerTune is a trademark of Texas Instruments.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
Copyright © 2010, Texas Instruments Incorporated  
 
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