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TLC1550I_14 PDF预览

TLC1550I_14

更新时间： 2024-11-21 02:58:39
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德州仪器 - TI /
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描述
Power Dissipation . . . 40 mW Max Advanced LinEPIC Single-Poly Process

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TLC1550I_14 数据手册

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SLAS043G − MAY 1991 − REVISED NOVEMBER 2003  
†
D
D
Power Dissipation . . . 40 mW Max  
J
OR DW PACKAGE  
(TOP VIEW)  
Advanced LinEPICSingle-Poly Process  
Provides Close Capacitor Matching for  
Better Accuracy  
REF+  
REF−  
ANLG GND  
AIN  
RD  
WR  
CLKIN  
CS  
D9  
1
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
14  
13  
2
D
D
D
D
D
Fast Parallel Processing for DSP and µP  
Interface  
3
4
Either External or Internal Clock Can Be  
Used  
ANLG V  
5
DD  
DGTL GND1  
DGTL GND2  
D8  
6
D7  
7
Conversion Time . . . 6 µs  
Total Unadjusted Error . . . 1 LSB Max  
CMOS Technology  
DGTL V  
D6  
8
DD1  
DGTL V  
DD2  
D5  
9
EOC  
D0  
D1  
D4  
D3  
D2  
10  
11  
12  
description  
The TLC1550x and TLC1551 are data acquisition  
†
Refer to the mechanical data for the JW  
package.  
analog-to-digital converters (ADCs) using a 10-bit,  
switched-capacitor, successive-approximation net-  
work. A high-speed, 3-state parallel port directly  
interfaces to a digital signal processor (DSP) or  
microprocessor (µP) system data bus. D0 through  
D9 are the digital output terminals with D0 being  
the least significant bit (LSB). Separate power  
terminals for the analog and digital portions  
minimize noise pickup in the supply leads.  
Additionally, the digital power is divided into two  
parts to separate the lower current logic from the  
higher current bus drivers. An external clock can be  
applied to CLKIN to override the internal system  
clock if desired.  
FK OR FN PACKAGE  
(TOP VIEW)  
4
3
2 1 28 27 26  
5
6
7
8
9
AIN  
ANLG V  
DGTL GND1  
25 CS  
24 D9  
DD  
D8  
NC  
D7  
D6  
D5  
23  
22  
21  
20  
19  
NC  
DGTL GND2  
DGTL V  
10  
11  
DD1  
DGTL V  
DD2  
The TLC1550I and TLC1551I are characterized for  
operation from −40°C to 85°C. The TLC1550M is  
characterized over the full military range of −55°C  
to 125°C.  
12 13 14 15 16 17 18  
NC − No internal connection  
AVAILABLE OPTIONS  
PACKAGE  
T
A
CERAMIC CHIP CARRIER PLASTIC CHIP CARRIER  
CERAMIC DIP  
(J)  
SOIC  
(DW)  
(FK)  
(FN)  
TLC1550IFN  
TLC1551IFN  
TLC1550IDW  
TLC1551IDW  
−40°C to 85°C  
−55°C to 125°C  
—
—
TLC1550MFK  
—
TLC1550MJ  
—
This device contains circuits to protect its inputs and outputs against damage due to high static voltages or electrostatic fields. These  
circuits have been qualified to protect this device against electrostatic discharges (ESD) of up to 2 kV according to MIL-STD-883C,  
Method 3015; however, it is advised that precautions be taken to avoid application of any voltage higher than maximum-rated  
voltages to these high-impedance circuits. During storage or handling, the device leads should be shorted together or the device  
should be placed in conductive foam. In a circuit, unused inputs should always be connected to an appropriated logic voltage level,  
preferably either V  
CC  
or ground.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Advanced LinEPIC is a trademark of Texas Instruments.  
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Copyright 2003, Texas Instruments Incorporated  
ꢍ ꢘ ꢙ ꢚ ꢛꢜ ꢝꢞ ꢟꢠ ꢞꢛ ꢡꢙ ꢢꢣ ꢤꢘ ꢟ ꢟꢛ ꢈꢆ ꢁꢉ ꢖꢒ ꢥ ꢉꢦꢧꢄ ꢦꢄꢇ ꢤꢢꢢ ꢙꢤ ꢚ ꢤ ꢡꢨ ꢟꢨꢚ ꢠ ꢤ ꢚ ꢨ ꢟꢨ ꢠꢟꢨ ꢜ  
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...16

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