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TL16C752CIRHBRG4 PDF预览

TL16C752CIRHBRG4

更新时间： 2024-01-20 11:45:05
品牌 Logo 应用领域
德州仪器 - TI 微控制器和处理器串行IO控制器通信控制器外围集成电路先进先出芯片数据传输时钟
页数 文件大小 规格书
50页 1235K
描述
DUAL UART WITH 64-BYTE FIFO

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TL16C752CIRHBRG4 技术参数

是否Rohs认证： 符合生命周期：Active
零件包装代码：QFN包装说明：HVQCCN, LCC32,.2SQ,20
针数：32Reach Compliance Code：compliant
HTS代码：8542.31.00.01风险等级：5.74
其他特性：ALSO OPERATES AT 1.8V/2.5V/3.3V SUPPLY地址总线宽度：3
边界扫描：NO最大时钟频率：48 MHz
通信协议：ASYNC, BIT最大数据传输速率：0.375 MBps
外部数据总线宽度：8JESD-30 代码：S-PQCC-N32
JESD-609代码：e4长度：5 mm
低功率模式：NO湿度敏感等级：3
串行 I/O 数：2端子数量：32
最高工作温度：85 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装代码：HVQCCN
封装等效代码：LCC32,.2SQ,20封装形状：SQUARE
封装形式：CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE峰值回流温度（摄氏度）：260
电源：1.8/5 V认证状态：Not Qualified
座面最大高度：1 mm子类别：Serial IO/Communication Controllers
最大压摆率：90 mA最大供电电压：5.5 V
最小供电电压：4.5 V标称供电电压：5 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：NO LEAD端子节距：0.5 mm
端子位置：QUAD处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：5 mmuPs/uCs/外围集成电路类型：SERIAL IO/COMMUNICATION CONTROLLER, SERIAL
Base Number Matches：1

TL16C752CIRHBRG4 数据手册

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TL16C752C  
DUAL UART  
WITH 64-BYTE FIFO  
www.ti.com  
SLLS646–MARCH 2008  
1
FEATURES  
•
ST16C654/654D Pin Compatible With  
Additional Enhancements (PFB Package Only)  
•
•
•
RS-485 Mode Support  
Support 1.8-V, 2.5-V, 3.3-V, or 5-V Supply  
•
•
•
•
•
Supports up to 24-MHz Crystal Input Clock  
(1.5 Mbps)  
Characterized for Operation From –40°C to  
85°C, Available in Commercial and Industrial  
Temperature Grades  
Supports up to 48-MHz Oscillator Input Clock  
(3 Mbps) for 5-V Operation  
•
•
Software-Selectable Baud-Rate Generator  
Supports up to 32-MHz Oscillator Input Clock  
(2 Mbps) for 3.3-V Operation  
Prescalable Provides Additional Divide-by-4  
Function  
Supports up to 24-MHz Input Clock (1.5 Mbps)  
for 2.5-V Operation  
•
•
Programmable Sleep Mode  
Programmable Serial Interface Characteristics  
Supports up to 16-MHz Input Clock (1 Mbps)  
for 1.8-V Operation  
–
–
5-, 6-, 7-, or 8-Bit Characters  
Even, Odd, or No Parity Bit Generation and  
Detection  
•
•
•
64-Byte Transmit FIFO  
64-Byte Receive FIFO With Error Flags  
–
1-, 1.5-, or 2-Stop Bit Generation  
Programmable and Selectable Transmit and  
Receive FIFO Trigger Levels for DMA and  
Interrupt Generation  
•
•
False Start Bit Detection  
Complete Status Reporting Capabilities in  
Both Normal and Sleep Mode  
•
•
Programmable Receive FIFO Trigger Levels for  
Software/Hardware Flow Control  
•
•
•
•
Line Break Generation and Detection  
Internal Test and Loopback Capabilities  
Fully Prioritized Interrupt System Controls  
Software/Hardware Flow Control  
–
–
Programmable Xon/Xoff Characters  
Modem Control Functions (CTS, RTS, DSR,  
DTR, RI, and CD)  
Programmable Auto-RTS and Auto-CTS  
•
•
Optional Data Flow Resume by Xon Any  
Character  
•
IrDA Capability  
DMA Signaling Capability for Both Received  
and Transmitted Data on PN Package  
DESCRIPTION  
The TL16C752C is a quad universal asynchronous receiver/transmitter (UART) with 64-byte FIFOs, automatic  
hardware/software flow control, and data rates up to 3 Mbps. It incorporates the functionality of four UARTs, each  
UART having its own register set and FIFOs. The four UARTs share only the data bus interface and clock  
source, otherwise they operate independently. Another name for the UART function is asynchronous  
communications element (ACE), and these terms are used interchangeably. The bulk of this document describes  
the behavior of each ACE, with the understanding that four such devices are incorporated into the TL16C752C.  
The TL16C752C offers enhanced features. It has a transmission control register (TCR) that stores received FIFO  
threshold level to start/stop transmission during hardware and software flow control. With the FIFO RDY register,  
the software gets the status of TXRDY/RXRDY for all four ports in one access. On-chip status registers provide  
the user with error indications, operational status, and modem interface control. System interrupts may be  
tailored to meet user requirements. An internal loopback capability allows onboard diagnostics.  
Each UART transmits data sent to it from the peripheral 8-bit bus on the TX signal and receives characters on  
the RX signal. Characters can be programmed to be 5, 6, 7, or 8 bits. The UART has a 64-byte receive FIFO and  
transmit FIFO and can be programmed to interrupt at different trigger levels. The UART generates its own  
desired baud rate based upon a programmable divisor and its input clock. It can transmit even, odd, or no parity  
and 1-, 1.5-, or 2-stop bits. The receiver can detect break, idle or framing errors, FIFO overflow, and parity errors.  
The transmitter can detect FIFO underflow. The UART also contains a software interface for modem control  
operations, and software flow control and hardware flow control capabilities.  
The TL16C752C is available in a 32-pin QFN (RHB) package. A 48-pin QFP (PFB) package will be available in  
late 2008.  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 2008, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
1234567...50

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TL16C752CIRHBRG4 替代型号

型号 品牌 替代类型 描述 数据表
TL16C752CIPFBR TI

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 DUAL UART WITH 64-BYTE FIFO
TL16C752CRHBR TI

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 DUAL UART WITH 64-BYTE FIFO
TL16C752CIRHBR TI

类似代替

 DUAL UART WITH 64-BYTE FIFO

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