Datasheet > TL16C2752FNG4

TL16C2752FNG4

更新时间： 2023-12-18 00:00:00

品牌	Logo	应用领域
德州仪器 - TI		通信时钟数据传输外围集成电路
页数	文件大小	规格书
25页	410K
描述
2 CHANNEL(S), 3Mbps, SERIAL COMM CONTROLLER, PQCC44, PLASTIC, LCC-44

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TL16C2752FNG4 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Obsolete	零件包装代码：	LCC
包装说明：	QCCJ, LDCC44,.7SQ	针数：	44
Reach Compliance Code：	unknown	HTS代码：	8542.31.00.01
风险等级：	5.68	其他特性：	ALSO OPERATES AT 1.8V/2.5V/3.3V SUPPLY
地址总线宽度：	3	边界扫描：	NO
最大时钟频率：	48 MHz	通信协议：	ASYNC, BIT
最大数据传输速率：	0.375 MBps	外部数据总线宽度：	8
JESD-30 代码：	S-PQCC-J44	JESD-609代码：	e4
长度：	16.585 mm	低功率模式：	NO
湿度敏感等级：	3	串行 I/O 数：	2
端子数量：	44	最高工作温度：	70 °C
最低工作温度：		封装主体材料：	PLASTIC/EPOXY
封装代码：	QCCJ	封装等效代码：	LDCC44,.7SQ
封装形状：	SQUARE	封装形式：	CHIP CARRIER
峰值回流温度（摄氏度）：	260	电源：	1.8/5 V
认证状态：	Not Qualified	座面最大高度：	4.57 mm
子类别：	Serial IO/Communication Controllers	最大供电电压：	5.5 V
最小供电电压：	4.5 V	标称供电电压：	5 V
表面贴装：	YES	技术：	CMOS
温度等级：	COMMERCIAL	端子面层：	Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：	J BEND	端子节距：	1.27 mm
端子位置：	QUAD	处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	16.585 mm	uPs/uCs/外围集成电路类型：	SERIAL IO/COMMUNICATION CONTROLLER, SERIAL
Base Number Matches：	1

TL16C2752FNG4 数据手册

TL16C2752

SLWS188A–JUNE 2006–REVISED SEPTEMBER 2008................................................................................................................................................ www.ti.com

DESCRIPTION

The TL16C2752 is a speed and functional upgrade of the TL16C2552. Since they are pinout and software

compatible, designs can easily migrate from the TL16C2552 to the TL16C2752 if needed. The additional

functionality within the TL16C2752 is accessed via an extended register set. Some of the key new features are

larger receive and transmit FIFOs, embedded IrDA encoders and decoders, RS-485 transceiver controls,

software flow control (Xon/Xoff) modes, programmable transmit FIFO thresholds, extended receive and transmit

threshold levels for interrupts, and extended receive threshold levels for flow control halt/resume operation.

The TL16C2752 is a dual universal asynchronous receiver and transmitter (UART). It incorporates the

functionality of two independent UARTs: each UART having its own register set and transmit and receive FIFOs.

The two UARTs share only the data bus interface and clock source, otherwise they operate independently.

Another name for the UART function is asynchronous communications element (ACE), and these terms will be

used interchangeably. The bulk of this document describes the behavior of each ACE, with the understanding

that two such devices are incorporated into the TL16C2752.

Functionally equivalent to the TL16C450 on power up or reset (single character or TL16C450 mode), each ACE

can be placed in an alternate FIFO mode. This relieves the CPU of excessive software overhead by buffering

received and to-be-transmitted characters. Each receiver and transmitter store up to 64 bytes in their respective

FIFOs, with the receive FIFO including three additional bits per byte for error status. In the FIFO mode,

selectable hardware or software autoflow control features can significantly reduce program overload and

increase system efficiency by automatically controlling serial data flow.

Each ACE performs serial-to-parallel conversions on data received from a peripheral device or modem and

stores the parallel data in its receive buffer or FIFO, and each ACE performs parallel-to-serial conversions on

data sent from its CPU after storing the parallel data in its transmit buffer or FIFO. The CPU can read the status

of either ACE at any time. Each ACE includes complete modem control capability and a processor interrupt

system that can be tailored to the application.

Each ACE includes a programmable baud rate generator capable of dividing a reference clock with divisors of

from 1 to 65535, thus producing a 16× or 8× internal reference clock for the transmitter and receiver logic. Each

ACE accommodates up to a 3-Mbaud serial data rate (48-MHz input clock). As a reference point, that speed

would generate a 333-ns bit time and a 3.33-＝s character time (for 8,N,1 serial data), with the internal clock

running at 48 MHz and 16× sampling.

Each ACE has a TXRDY and RXRDY (via MF) output that can be used to interface to a DMA controller.

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Product Folder Link(s): TL16C2752

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与TL16C2752FNG4相关器件

型号	品牌	获取价格	描述	数据表
TL16C2752FNR	TI	获取价格	2 CHANNEL(S), 3Mbps, SERIAL COMM CONTROLLER, PQCC44, PLASTIC, LCC-44
TL16C2752IFN	TI	获取价格	具有 64 字节 FIFO 的 1.8V 至 5V 双路 UART \| FN \| 44 \|
TL16C2752IFNG4	TI	获取价格	1.8-V to 5-V Dual UART with 64-Byte FIFOs 44-PLCC -40 to 85
TL16C2752IFNR	TI	获取价格	暂无描述
TL16C2752RHB	TI	获取价格	2 CHANNEL(S), 3Mbps, SERIAL COMM CONTROLLER, PQCC32, PLASTIC, QFN-32
TL16C450	TI	获取价格	ASYNCHRONOUS COMMUNICATIONS ELEMENT
TL16C450FN	TI	获取价格	ASYNCHRONOUS COMMUNICATIONS ELEMENT
TL16C450FNG4	TI	获取价格	Single UART Without FIFO 44-PLCC 0 to 70
TL16C450FNR	TI	获取价格	Single UART Without FIFO 44-PLCC 0 to 70
TL16C450N	TI	获取价格	ASYNCHRONOUS COMMUNICATIONS ELEMENT

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