Datasheet > TDA10025HN/C1,518

TDA10025HN/C1,518

更新时间： 2024-11-02 20:09:07

品牌	Logo	应用领域
恩智浦 - NXP		/
页数	文件大小	规格书
8页	113K
描述
TDA10025HN - Dual cable demodulator QFN 48-Pin

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TDA10025HN/C1,518 技术参数

TDA10025HN

Dual cable demodulator

Rev. 1 — 22 August 2011

Product short data sheet

1. General description

The TDA10025HN is a Dual Cable Downstream Processor.

The Cable Downstream Processor (CDP) implements the physical interfaces and

protocols required to provide the highest quality services of an in-band DOCSIS,

EuroDOCSIS, DVB and OpenCable Set-Top Box (STB). The downstream signals are

digitized by 12-bit ADC and passed to the Demod and Forward Error Correction (FEC)

blocks, which do all the cable physical layer processing. This processing includes

demodulating and Annex A (Europe), Annex B (US) or Annex C (Japan) FEC for the

in-band data.

2. Features and benefits

 QPSK, 16 QAM, 32 QAM, 64 QAM, 128 QAM and 256 QAM Demodulator

 ITU-T J83 Annex A, B and C FEC

 Transport Stream Multiplex Frame (TSMF) module for Annex C compliance

 Time interleaved parallel mode or serial mode for Transport Stream (TS) interface

 On chip PLL for crystal frequency multiplication (16 MHz external)

 Reuse of the tuner clock, saving one crystal

 Embedded 12-bit ADC

 3.3 V and 1.2 V power supplies

 Low power < 235 mW for dual stream operation

 Small size package

 Low cost Bill Of Material (BOM)

12 3 4 5 6 7 8

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型号	品牌	获取价格	描述	数据表
TDA10025HN/C1,551	NXP	获取价格	TDA10025HN - Dual cable demodulator QFN 48-Pin
TDA10025HN/C1,557	NXP	获取价格	TDA10025HN - Dual cable demodulator QFN 48-Pin
TDA10025HN/C1/S3Y	NXP	获取价格	TDA10025HN - Dual cable demodulator QFN 48-Pin
TDA1003A	NXP	获取价格	MOTOR REGULATOR AND BIAS/ERASE OSCILLATOR CIRCUIT
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TDA10045H	NXP	获取价格	DVB-T channel receiver
TDA10046HT	NXP	获取价格	Single-chip DVB-T channel
TDA1005A	NXP	获取价格	FREQUENCY MULTIPLEX PLL STEREO DECODER
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