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TC74HC138AP_07 PDF预览

TC74HC138AP_07

更新时间: 2024-11-05 05:04:11
品牌 Logo 应用领域
东芝 - TOSHIBA /
页数 文件大小 规格书
9页 336K
描述
3-to-8 Line Decoder

TC74HC138AP_07 数据手册

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TC74HC138AP/AF/AFN  
TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic  
TC74HC138AP,TC74HC138AF,TC74HC138AFN  
3-to-8 Line Decoder  
Note: xxxFN (JEDEC SOP) is not available in  
Japan.  
The TC74HC138A is a high speed CMOS 3-to-8 DECODER  
fabricated with silicon gate C2MOS technology.  
TC74HC138AP  
It achieves the high speed operation similar to equivalent  
LSTTL while maintaining the CMOS low power dissipation.  
When the device is enabled, 3 Binary Select inputs (A, B and  
C) determine which one of the outputs ( Y0 - Y7 ) will go low.  
When enable input G1 is held low or either G2A or G2B is  
held high, decoding function is inhibited and all outputs go high.  
G1, G2A , and G2B inputs are provided to ease cascade  
connection and for use as an address decoder for memory  
systems.  
TC74HC138AF  
All inputs are equipped with protection circuits against static  
discharge or transient excess voltage.  
Features  
High speed: t = 16 ns (typ.) at V  
= 5 V  
pd  
CC  
Low power dissipation: I  
= 4 μA (max) at Ta = 25°C  
CC  
High noise immunity: V  
= V  
= 28% V  
(min)  
NIH  
NIL  
CC  
Output drive capability: 10 LSTTL loads  
Symmetrical output impedance: |I | = I  
TC74HC138AFN  
= 4 mA (min)  
OL  
OH  
Balanced propagation delays: t  
t
pHL  
pLH  
Wide operating voltage range: V  
(opr) = 2 to 6 V  
CC  
Pin and function compatible with 74LS138  
Pin Assignment  
Weight  
DIP16-P-300-2.54A  
SOP16-P-300-1.27A  
SOL16-P-150-1.27  
: 1.00 g (typ.)  
: 0.18 g (typ.)  
: 0.13 g (typ.)  
1
2007-10-01  

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