Datasheet > TC74HC139AP_07

TC74HC139AP_07

更新时间： 2024-11-06 05:04:11

品牌	Logo	应用领域
东芝 - TOSHIBA		解码器
页数	文件大小	规格书
8页	284K
描述
Dual 2-to-4 Line Decoder

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中文翻译

获取价格

数据手册

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TC74HC139AP_07 数据手册

TC74HC139AP/AF/AFN

TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic

TC74HC139AP,TC74HC139AF,TC74HC139AFN

Dual 2-to-4 Line Decoder

Note: xxxFN (JEDEC SOP) is not available in

Japan.

The TC74HC139A is a high speed CMOS 2-to-4 LINE

DECODER/DEMULTIPLEXER fabricated with silicon gate

C²MOS technology.

TC74HC139AP

It achieves the high speed operation similar to equivalent

LSTTL while maintaining the CMOS low power dissipation.

The active low enable input can be used for gating or it can be

used as a data input for demultiplexing applications.

When the enable input is held “H”, all four outputs are fixed at

a high logic level independent of the other inputs.

All inputs are equipped with protection circuits against static

discharge or transient excess voltage.

TC74HC139AF

Features

•

High speed: t = 16 ns (typ.) at V

= 5 V

Low power dissipation: I

= 4 μA (max) at Ta = 25°C

High noise immunity: V

= V

= 28% V

(min)

NIH

NIL

Output drive capability: 10 LSTTL loads

Symmetrical output impedance: |I | = I

= 4 mA (min)

∼

−

Balanced propagation delays: t

pHL

pLH

TC74HC139AFN

Wide operating voltage range: V

(opr) = 2~6 V

Pin and function compatible with 74LS139

Pin Assignment

Weight

DIP16-P-300-2.54A

SOP16-P-300-1.27A

SOL16-P-150-1.27

: 1.00 g (typ.)

: 0.18 g (typ.)

: 0.13 g (typ.)

2007-10-01

12 3 4 5 6 7 8

中文翻译

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