TC74ACT112F(F)

更新时间： 2024-02-04 01:25:13

品牌	Logo	应用领域
东芝 - TOSHIBA		触发器锁存器逻辑集成电路光电二极管
页数	文件大小	规格书
9页	312K
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数据手册

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TC74ACT112F(F) 数据手册

TC74ACT112P/F/FN

TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic

TC74ACT112P,TC74ACT112F,TC74ACT112FN

Dual J-K Flip Flop with Preset and Clear

Note: xxxFN (JEDEC SOP) is not available in

Japan.

The TC74ACT112 is an advanced high speed CMOS DUAL J-K

FLIP FLOP fabricated with silicon gate and double-layer metal

wiring C²MOS technology.

TC74ACT112P

It achieves the high speed operation similar to equivalent

Bipolar Schottky TTL while maintaining the CMOS low power

dissipation.

This device may be used as a level converter for interfacing

TTL or NMOS to High Speed CMOS. The inputs are compatible

with TTL, NMOS and CMOS output voltage levels.

In accordance with the logic level given J and K input this

device changes state on negative going transition of the clock

TC74ACT112F

pulse. CLEAR and PRESET are independent of the clock and

accomplished by a low logic level on the corresponding input.

All inputs are equipped with protection circuits against static

discharge or transient excess voltage.

Features

•

High speed: f

= 175 MHz (typ.) at V

= 5 V

max

Low power dissipation: I

= 4 μA (max) at Ta = 25°C

TC74ACT112FN

Compatible with TTL outputs: V = 0.8 V (max)

= 2.0 V (min)

•

Symmetrical output impedance: |I | = I

= 24 mA (min)

Capability of driving 50 Ω

transmission lines.

∼

−

pHL

•

Balanced propagation delays: t

pLH

Pin and function compatible with 74F112

Pin Assignment

Weight

DIP16-P-300-2.54A

SOP16-P-300-1.27A

SOL16-P-150-1.27

: 1.00 g (typ.)

: 0.18 g (typ.)

: 0.13 g (typ.)

2007-10-01

12 3 4 5 6 7...9

中文翻译

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