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TC74ACT138FN-ELP PDF预览

TC74ACT138FN-ELP

更新时间: 2024-02-23 00:25:24
品牌 Logo 应用领域
东芝 - TOSHIBA 解码器驱动器逻辑集成电路光电二极管
页数 文件大小 规格书
9页 275K
描述
IC ACT SERIES, OTHER DECODER/DRIVER, INVERTED OUTPUT, PDSO16, 0.150 INCH, PLASTIC, SOIC-16, Decoder/Driver

TC74ACT138FN-ELP 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:DIP包装说明:DIP, DIP16,.3
针数:16Reach Compliance Code:unknown
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.82其他特性:3 ENABLE INPUTS
系列:ACT输入调节:STANDARD
JESD-30 代码:R-PDIP-T16长度:19.25 mm
负载电容(CL):50 pF逻辑集成电路类型:OTHER DECODER/DRIVER
最大I(ol):0.024 A功能数量:1
端子数量:16最高工作温度:85 °C
最低工作温度:-40 °C输出极性:INVERTED
封装主体材料:PLASTIC/EPOXY封装代码:DIP
封装等效代码:DIP16,.3封装形状:RECTANGULAR
封装形式:IN-LINE电源:5 V
Prop。Delay @ Nom-Sup:11.5 ns传播延迟(tpd):11.5 ns
认证状态:Not Qualified座面最大高度:4.45 mm
子类别:Decoder/Drivers最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:NO技术:CMOS
温度等级:INDUSTRIAL端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
宽度:7.62 mm

TC74ACT138FN-ELP 数据手册

 浏览型号TC74ACT138FN-ELP的Datasheet PDF文件第2页浏览型号TC74ACT138FN-ELP的Datasheet PDF文件第3页浏览型号TC74ACT138FN-ELP的Datasheet PDF文件第4页浏览型号TC74ACT138FN-ELP的Datasheet PDF文件第5页浏览型号TC74ACT138FN-ELP的Datasheet PDF文件第6页浏览型号TC74ACT138FN-ELP的Datasheet PDF文件第7页 
TC74ACT138P/F/FN/FT  
TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic  
TC74ACT138P,TC74ACT138F,TC74ACT138FN,TC74ACT138FT  
3-to-8 Line Decoder  
Note: xxxFN (JEDEC SOP) is not available in  
Japan.  
The TC74ACT138 is an advanced high speed CMOS 3-to-8  
LINE DECODER fabricated with silicon gate and double-layer  
metal wiring C2MOS technology.  
TC74ACT138P  
It achieves the high speed operation similar to equivalent  
Bipolar Schottky TTL while maintaining the CMOS low power  
dissipation.  
This device may be used as a level converter for interfacing  
TTL or NMOS to High Speed CMOS. The inputs are compatible  
with TTL, NMOS and CMOS output voltage levels.  
When the device is enabled, 3 Binary Select inputs (A, B and  
C) determine which one of the outputs ( Y0 - Y7 ) will go low.  
TC74ACT138F  
When enable input G1 is held low or either G2A or G2B is  
held high, decoding function is inhibited and all outputs go high.  
G1, G2A , and G2B inputs are provided to ease cascade  
connection and for use as an address decoder for memory  
systems.  
All inputs are equipped with protection circuits against static  
discharge or transient excess voltage.  
Features  
TC74ACT138FN  
High speed: t = 6.0 ns (typ.) at V  
= 5 V  
pd  
CC  
Low power dissipation: I  
= 8 μA (max) at Ta = 25°C  
CC  
Compatible with TTL outputs: V = 0.8 V (max)  
IL  
V
IH  
= 2.0 V (min)  
Symmetrical output impedance: |I | = I  
= 24 mA (min)  
OH  
OL  
Capability of driving 50 Ω  
transmission lines.  
t
pHL  
Balanced propagation delays: t  
pLH  
TC74ACT138FT  
Pin and function compatible with 74F138  
Weight  
DIP16-P-300-2.54A  
SOP16-P-300-1.27A  
SOL16-P-150-1.27  
TSSOP16-P-0044-0.65A  
: 1.00 g (typ.)  
: 0.18 g (typ.)  
: 0.13 g (typ.)  
: 0.06 g (typ.)  
1
2007-10-01  

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