Datasheet > T2316405A-70

T2316405A-70

更新时间： 2022-11-26 03:13:27

品牌	Logo	应用领域
TMT		/
页数	文件大小	规格书
14页	137K
描述
4M x 4 DYNAMIC RAM EDO PAGE MODE

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T2316405A-70 数据手册

T2316405A

Preliminary T2316407A

DC CHARACTERISTICS

(Ta = 0 to 70 ) T2316405A-10 Vcc = 2.6V 0.2V, Vss = 0V

T2316407A-50/60/70 Vcc =3.3V 0.3V, Vss = 0V

-50

-60

-70

-10

Parameter

Symbol

Unit

Test Condition

0V Vin Vcc+ 0.3V

Min Ma Min Ma Min Ma Min Ma

Input Leakage Current

-5

Other pins = 0V

0V Vout Vcc

Output Leakage

Current

Dout = disable

High Iout= -2.0mA

Output High Voltage

Output Low Voltage

2.0

Low Iout=2.0mA

0.8

RAS , CAS cycling

Operating Current

Standby Current

Icc1

50 mA

=min

TTL interface,

mA RAS CAS

Icc2

D =High-Z

OUT

CMOS interface,

Icc3

Icc4

Icc5

Icc6

0.5

0.5 mA

50 mA

RAS CAS

> Vcc-0.2V

EDO Page Mode

Current

RAS

=VIL,

CAS

cycling, t = min

RAS

CAS

cycling, RC = min

RAS

=VIH,

-only refresh

Current

RAS ,CAS cycling,

CAS

RAS

Before

Refresh Current

= min

Note: Icc depends on output load condition when the device is selected.

Icc max is specified at the output open condition, Icc is specified as an average current.

CAPACITANCE

(Ta =25 C, f = 1M HZ, T2316405A-10 Vcc = 2.6V, T2316407A-50/60/70 Vcc =3.3V)

Parameter

Input Capacitance

(address)

Symbol

Typ

Max

Unit

Input Capacitance

RAS CAS WE OE

)

(

Output Capacitance

(data-in/out)

I/O

Taiwan Memory Technology, Inc. reserves the right P. 4

to change products or specifications without notice.

Publication Date: APR. 2001

Revision:0.B

1 2 345 6 7...14

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