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T2316405A-70 PDF预览

T2316405A-70

更新时间: 2024-02-21 18:47:36
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14页 137K
描述
4M x 4 DYNAMIC RAM EDO PAGE MODE

T2316405A-70 数据手册

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T2316405A  
TE  
tm
CH  
Preliminary T2316407A  
Notes:  
1. An initial pause of 200us is required after  
11. t  
,
t
,
t
and  
t
are  
WCS RWD  
AWD  
CWD  
RAS  
power-up followed by eight  
refresh  
only or CBR) before proper  
restrictive operating parameters in LATE  
WRITE and READ-MODIFY-WRITE cycles  
RAS  
cycles (  
only. If t  
WCS  
EARLY WRITE cycle and the data output will  
remain an open circuit throughout the entire  
t (min), the cycle is an  
³
WCS  
device operation is assured. The eight RAS  
cycle wake-ups should be repeated any time  
the t  
refresh requirement is exceeded.  
REF  
cycle. If t  
t
(min), t  
³
³
RWD  
(min) and t  
RWD  
AWD  
2. V (2.0V) and V (0.8V) are reference  
IH IL  
t
t (min), the  
CWD  
³
AWD  
CWD  
levels for measuring timing of input signals.  
Transition times are measured between  
cycle is READ-WRITE and the data output  
will contain data read from the selected cell. If  
neither of the above conditions is met, the state  
V
and V .  
IL(0.8V)  
IH(2.0V)  
3. In addition to meet the transition rate  
specification, all input signals must transit  
CAS  
of I/O (at access time and until  
and  
RAS or OE go back to V ) is indeterminate.  
IH  
taken low after  
between V and V in a monotonic manner.  
IH  
IL  
OE  
WE  
CAS  
OE  
held high and  
4. Assume that t  
< t  
(max). If t  
is  
RCD RCD RCD  
goes low result in a LATE WRITE (  
controlled) cycle.  
-
greater than the maximum recommended value  
shown in this table, t will increase by the  
RAC  
exceeds the value shown.  
CAS  
12. These parameters are referenced to  
amount that t  
RCD  
5. Assume that t  
leading edge in EARLY WRITE cycles and  
WE leading edge in LATE WRITE or READ-  
MODIFY-WRITE cycles.  
t
(max) .  
³
RCD RCD  
6. Enables on-chip refresh and address counters.  
7. Operation within the t (max) limit ensures  
RCD  
13. During a READ cycle, if OE is low then taken  
that t  
(max) can be met. t  
(max) is  
is  
RAC  
RCD  
CAS  
HIGH before  
OE  
if  
WRITE  
goes high, I/O goes open,  
is tied permanently low, a LATE  
or READ-MODIFY-WRITE  
specified as a reference point only; if t  
RCD  
greater than the specified t  
access time is controlled by t  
(max) limit,  
RCD  
CAC  
.
operation is not possible.  
8. Operation within the t  
limit ensures that  
RAD  
WE  
14. WRITE command is defined as  
going low.  
t
(max) can be met. t  
(max) is  
is  
RAC RAD  
15. LATE WRITE and READ-MODIFY-WRITE  
cycles must have both t and t met  
specified as a reference point only; if t  
RAD  
OFF2 OEH  
greater than the specified t  
(max) limit,  
RAD  
( OE high during WRITE cycle) in order to  
ensure that the output buffers will be open  
during the WRITE cycles.  
access time is controlled by t  
.
AA  
must be satisfied for a  
9. Either t  
RCH  
or t  
RRH  
READ cycle.  
16. The I/Os open during READ cycles once  
10. t (max) defines the time at which the  
OFF1  
output achieves the open circuit condition; it is  
not a reference to V or V  
t
or t  
OFF2  
occur.  
OFF1  
.
OH OL  
Taiwan Memory Technology, Inc. reserves the right P. 7  
to change products or specifications without notice.  
Publication Date: APR. 2001  
Revision:0.B  

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