TE
tmCH
T2316160A
1024K x 16 DYNAMIC RAM
DRAM
FAST PAGE MODE
FEATURES
GENERAL DESCRIPTION
• Industry-standard x 16 pinouts and timing
functions.
• Single 5V (±10%) power supply.
• All device pins are TTL- compatible.
• 1K-cycle refresh in 16ms.
The T2316160A is a randomly accessed solid state
memory containing 16,777,216 bits organized in a
x16 configuration. The T2316160A has both
BYTE WRITE and WORD WRITE access cycles
via two CAS pins. It offers Fast Page mode with
Extended Data Output.
RAS
CAS
BEFORE
• Refresh modes:
only,
(CBR) and HIDDEN.
RAS
• BYTE WRITE and BYTE READ access cycles.
CAS
The T2316160A
determined by the first
by the last to transition back high. Use only one of
CAS
function and timing are
CAS
to transition low and
OPTION
TIMING
MARKING
the two
and leave the other staying high
45ns
60ns
-45
-60
during WRITE will result in a BYTE WRITE.
CASL to transition low in a WRITE cycle will
write data into the lower byte (DQ0~DQ7), and
PACKAGE
42-pin SOJ
44/50-pin TSOPII
J
S
CASH
transiting low will write data into the
upper byte (DQ8~DQ15).
PIN ASSIGNMENT ( Top View )
VDD
DQ0
DQ1
DQ2
DQ3
VDD
Vss
1
50
49
48
47
46
45
44
43
42
41
40
DQ15
DQ14
DQ13
DQ12
Vss
2
V
DD
Vss
1
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
3
DQ0
DQ1
DQ2
DQ3
DQ15
DQ14
DQ13
DQ12
Vss
4
2
5
3
6
4
DQ4
DQ5
DQ6
DQ7
NC
DQ11
DQ10
DQ9
DQ8
NC
7
5
8
V
DD
6
9
DQ4
DQ5
DQ6
DQ7
NC
DQ11
DQ10
DQ9
DQ8
NC
7
10
11
8
9
10
11
12
13
14
15
16
17
18
19
20
21
NC
CASL
CASH
OE
NC
NC
WE
RAS
NC
NC
A0
NC
CASL
CASH
OE
A9
15
16
17
18
19
20
21
22
23
24
25
36
35
34
33
32
31
30
29
28
27
26
WE
RAS
NC
A9
NC
A8
A8
A0
A7
A7
A1
A6
A1
A6
A2
A5
A2
A5
A3
A4
A3
A4
V
DD
Vss
VDD
Vss
Taiwan Memory Technology, Inc. reserves the right P. 1
to change products or specifications without notice.
Publication Date: APR. 2002
Revision:A