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SY69753AL

更新时间： 2024-11-09 03:12:43

品牌	Logo	应用领域
麦瑞 - MICREL		时钟
页数	文件大小	规格书
13页	494K
描述
3.3V, 125Mbps, 155Mbps Clock and Data Recovery

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数据手册

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SY69753AL 数据手册

SY69753AL

3.3V, 125Mbps, 155Mbps Clock

and Data Recovery

General Description

Features

The SY69753AL is a complete Clock Recovery and

Data Retiming integrated circuit for OC-3/STS-3

applications at 155Mbps NRZ. The device is ideally

suited for SONET/SDH/ATM applications and other

high-speed data transmission systems.

• 3.3V power supply

• SONET/SDH/ATM compatible

• Clock and data recovery for 125Mbps/155Mbps NRZ

data stream

• Two on-chip PLLs: one for clock generation and

Clock recovery and data retiming is performed by

synchronizing the on-chip VCO directly to the incoming

data stream. The VCO center frequency is controlled by

the reference clock frequency and the selected divide

ratio. On-chip clock generation is performed through the

use of a frequency multiplier PLL with a byte rate source

as reference.

another for clock recovery

• Selectable reference frequencies

• Differential PECL high-speed serial I/O

• Line receiver input: no external buffering needed

• Link fault indication

• 100k ECL compatible I/O

• Industrial temperature range (–40°C to +85°C)

The SY69753AL also includes a link fault detection

circuit.

• Lower power: fully compatible with Micrel’s

Datasheets and support documentation can be found on

Micrel’s web site at: www.micrel.com.

SY87701V, but with 30% less power

• Available in 32-pin EPAD-TQFP

Applications

• Ethernet media converter(m)

• SONET/SDH/ATM OC-3

• Proprietary architecture at 120Mbps to 180Mbps

Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com

M9999-111406-D

hbwhelp@micrel.com or (408) 955-1690

November 2006

12 3 4 5 6 7...13

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