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SY10EL89ZGTR PDF预览

SY10EL89ZGTR

更新时间: 2024-11-02 19:59:55
品牌 Logo 应用领域
美国微芯 - MICROCHIP 驱动光电二极管接口集成电路驱动器
页数 文件大小 规格书
5页 146K
描述
LINE DRIVER, PDSO8, 0.150 INCH, SOIC-8

SY10EL89ZGTR 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Transferred零件包装代码:SOIC
包装说明:SOP,针数:8
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.15
差分输出:YES驱动器位数:1
输入特性:DIFFERENTIAL接口集成电路类型:LINE DRIVER
接口标准:GENERAL PURPOSEJESD-30 代码:R-PDSO-G8
JESD-609代码:e4长度:4.93 mm
湿度敏感等级:1标称负供电电压:-5 V
功能数量:1端子数量:8
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):260认证状态:Not Qualified
座面最大高度:1.73 mm表面贴装:YES
温度等级:INDUSTRIAL端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:40
最大传输延迟:0.44 ns宽度:3.94 mm
Base Number Matches:1

SY10EL89ZGTR 数据手册

 浏览型号SY10EL89ZGTR的Datasheet PDF文件第2页浏览型号SY10EL89ZGTR的Datasheet PDF文件第3页浏览型号SY10EL89ZGTR的Datasheet PDF文件第4页浏览型号SY10EL89ZGTR的Datasheet PDF文件第5页 
COAXIAL  
CABLE DRIVER  
SY10EL89  
FINAL  
FEATURES  
DESCRIPTION  
375ps propagation delay  
The SY10EL89 is a differential fanout gate specifically  
designed to drive coaxial cables. The device is especially  
useful in Digital Video Broadcast applications. For this  
application, since the system is polarity-free, each output  
of the device can be used as an independent driver.  
The driver boasts a voltage gain of approximately 40  
and produces output swings twice as large as a standard  
ECL output. When driving a coaxial cable, proper  
termination is required at both ends of the line to minimize  
signal loss. The 1.6V output swings allow for termination  
at both ends of the cable while maintaining the required  
800mV swing at the receiving end of the cable. Because  
of the larger output swings, the device cannot be  
terminated into the standard –2.0V. All of the DC  
parameters are tested with a 50to –3.0V load. The  
driver accepts a standard differential ECL input and can  
run off the Digital Video Broadcast standard –5.0V supply.  
1.6V output swings  
Internal 75Kinput pull-down resistors  
Available in 8-pin SOIC package  
PIN CONFIGURATION/BLOCK DIAGRAM  
1
2
3
4
8
7
6
5
VCC  
Q
Q
Q
Q
0
0
1
1
D
D
PIN NAMES  
V
EE  
Pin  
Function  
D
Data Inputs  
Data Outputs  
SOIC  
TOP VIEW  
Q0, Q1  
Rev.: G  
Amendment:/0  
Issue Date: February 2003  
1

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