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SY10ELT20V PDF预览

SY10ELT20V

更新时间: 2024-11-01 22:59:23
品牌 Logo 应用领域
麦瑞 - MICREL /
页数 文件大小 规格书
4页 54K
描述
5V/3.3V TTL-to-DIFFERENTIAL PECL TRANSLATOR

SY10ELT20V 数据手册

 浏览型号SY10ELT20V的Datasheet PDF文件第2页浏览型号SY10ELT20V的Datasheet PDF文件第3页浏览型号SY10ELT20V的Datasheet PDF文件第4页 
5V/3.3V  
TTL-to-DIFFERENTIAL  
PECL TRANSLATOR  
ClockWorks™  
SY10ELT20V  
SY100ELT20V  
FEATURES  
DESCRIPTION  
3.3V and 5V power supply options  
300ps typical propagation delay  
Low power  
The SY10/100ELT20V is a single TTL-to-differential  
PECL translators. Because PECL (Positive ECL) levels  
are used, either +5V or +3.3V and ground are required.  
The small outline 8-lead SOIC package and low skew  
single gate design make the ELT20V ideal for applications  
that require the translation of a clock or data signal where  
minimal space, low power, and low cost are critical.  
The ELT20V is available in both ECL standards: the  
10ELT is compatible with positive ECL 10H logic levels,  
while the 100ELT is compatible with positive ECL 100K  
logic levels.  
Differential PECL output  
PNP TTL input for minimal loading  
Flow-through pinouts  
Available in 8-pin SOIC package  
PIN CONFIGURATION/BLOCK DIAGRAM  
PIN NAMES  
Pin  
Function  
Differential PECL Output  
TTL Input  
NC  
Q
1
2
3
4
8
7
6
5
VCC  
D
Q
TTL  
D
PECL  
Q
NC  
GND  
VCC  
GND  
+5V/+3.3V Supply  
Ground  
NC  
SOIC  
TOP VIEW  
Rev.: A  
Amendment:/0  
Issue Date: December1999  
1

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