SY10E142

更新时间： 2024-09-27 22:59:23

品牌	Logo	应用领域
麦瑞 - MICREL		移位寄存器
页数	文件大小	规格书
4页	75K
描述
9-BIT SHIFT REGISTER

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中文翻译

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数据手册

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SY10E142 数据手册

9-BIT SHIFT

SY10E142

SY100E142

FEATURES

DESCRIPTION

■ 700MHz min. shift frequency

■ Extended 100E VEE range of –4.2V to –5.5V

■ 9 bits wide for byte-parity applications

■ Asynchronous Master Reset

■ Dual clocks

The SY10/100E142 are high-speed 9-bit shift registers

designed for use in new, high-performance ECL systems.

The E142 can accept serial or parallel data to be shifted out

in one direction as both serial and parallel outputs. The

nine inputs, D0-D8, accept parallel input data, while S-IN

accepts serial input data.

The SEL (Select) control pin serves to determine the

modeofoperation, eitherSHIFTorLOAD. Theshiftdirection

is from bit 0 to bit 8. The input data has to meet the set-up

time before being clocked into the nine input registers on

the rising edge of CLK1 or CLK2. Shifting is also performed

on the rising edge of either CLK1 or CLK2. The MR (Master

Reset) control signal asynchronously resets all nine

registers to a logic LOW when a logic HIGH is applied to

MR.

■ Fully compatible with industry standard 10KH,

100K ECL levels

■ Internal 75KΩ input pulldown resistors

■ Fully compatible with Motorola MC10E/100E142

■ Available in 28-pin PLCC package

BLOCK DIAGRAM

The E142 is designed for applications such as diagnostic

scan registers, parallel-to-serial conversions and is also

suitable for byte-wide parity.

S-IN

D Q

PIN CONFIGURATION

25 24 23 22 21 20 19

CLK

VCC

PLCC

TOP VIEW

J28-1

VEE

S-IN

VCCO

10 11

PIN NAMES

D Q

D0-D8

S-IN

Function

Parallel Data Inputs

Serial Data Input

Mode Select Input

Clock Inputs

SEL

CLK1, CLK2

SEL

Master Reset

CLK1

CLK2

Q0-Q8

VCCO

Data Outputs

VCC to Output

Rev.: C

Amendment: /1

Issue Date: February, 1998

12 3 4

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