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SY100EPT23LZC PDF预览

SY100EPT23LZC

更新时间: 2024-11-04 22:14:27
品牌 Logo 应用领域
麦瑞 - MICREL 转换器电平转换器驱动程序和接口锁存器接口集成电路光电二极管
页数 文件大小 规格书
8页 76K
描述
3.3V DUAL DIFFERENTIAL LVPECL-to-LVTTL TRANSLATOR

SY100EPT23LZC 技术参数

是否Rohs认证:不符合生命周期:Obsolete
零件包装代码:SOIC包装说明:PLASTIC, SOIC-8
针数:8Reach Compliance Code:not_compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.12Is Samacsys:N
最大延迟:2.5 ns接口集成电路类型:PECL TO TTL TRANSLATOR
JESD-30 代码:R-PDSO-G8JESD-609代码:e0
长度:4.93 mm湿度敏感等级:1
位数:1功能数量:2
端子数量:8最高工作温度:85 °C
最低工作温度:输出锁存器或寄存器:NONE
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP8,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):240电源:3.3 V
认证状态:Not Qualified座面最大高度:1.73 mm
子类别:Level Translators最大供电电压:3.6 V
最小供电电压:3 V标称供电电压:3.3 V
表面贴装:YES技术:ECL100K
温度等级:COMMERCIAL EXTENDED端子面层:Tin/Lead (Sn85Pb15)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
宽度:3.94 mmBase Number Matches:1

SY100EPT23LZC 数据手册

 浏览型号SY100EPT23LZC的Datasheet PDF文件第2页浏览型号SY100EPT23LZC的Datasheet PDF文件第3页浏览型号SY100EPT23LZC的Datasheet PDF文件第4页浏览型号SY100EPT23LZC的Datasheet PDF文件第5页浏览型号SY100EPT23LZC的Datasheet PDF文件第6页浏览型号SY100EPT23LZC的Datasheet PDF文件第7页 
3.3V DUAL DIFFERENTIAL  
LVPECL-to-LVTTL  
TRANSLATOR  
SY100EPT23L  
FEATURES  
DESCRIPTION  
3.3V power supply  
The SY100EPT23L is a dual differential LVPECL-to-  
LVTTL translator. Because LVPECL (Low Voltage Positive  
ECL) levels are used, only +3.3V and ground are required.  
The tiny 8-pin MSOP and dual-gate design of the EPT23L  
makes it ideal for applications which require the  
translation of a clock and data signal.  
1.9ns typical propagation delay  
Maximum frequency > 275MHz  
Differential LVPECL inputs  
24mA LVTTL outputs  
The EPT23L is available in only the ECL 100K  
standard. Since there are no LVPECL outputs or an  
Flow-through pinouts  
Internal input resistors: pulldown on D, pulldown  
external V  
reference, the EPT23L does not require  
BB  
and pullup on /D  
both ECL standard versions. The inputs can accept 10K  
voltage levels and any standard differential LVPECL input  
Q output will default LOW with inputs open or at  
Ground  
referenced from a V  
of +3.3V  
CC  
Available in 8-pin MSOP and SOIC packages  
PIN CONFIGURATION/BLOCK DIAGRAM  
PIN NAMES  
Pin  
Q0, Q1  
Function  
D0  
/D0  
/D1  
D1  
1
2
3
4
8
7
6
5
VCC  
Q0  
LVTTL Outputs  
Differential LVPECL Inputs  
Positive Supply  
Ground  
D0, /D0, D1, /D1  
VCC  
LVPECL  
LVTTL  
Q1  
GND  
GND  
(Available in 8-pin SOIC and 8-pin MSOP)  
Rev.: A  
Amendment: 1  
1
Issue Date: July 2000  

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